Transcript Verilog Tutorial I

ENEE 408C Lab
Capstone Project: Digital System Design
Verilog Tutorial
Class Web Site:
http://www.ece.umd.edu/class/enee408c
Modules and Primitives
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Modules
The user-defined components
module fulladder (<port list>)
…
endmodule
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Primitives
Pre-defined components
nand g(<port_list>)
•Have to specify inputs and
outputs
•Can have multiple outputs
•Module instantiation
fulladder f(<port_list);
•First port is output
•Have only one output
•Primitives instantiation
nand g(<port_list>);
Registers and Nets
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reg
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wire
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–
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stores 1 bit information by default
similar to C/C++ variables in syntax
used on both LHS and RHS in procedural assignment
cannot be used on LHS in continuous assignment
default width is 1 bit
establish connectivity between two components
driven by the components it connects to
used on LHS in continuous assignment
cannot be used on LHS in procedural assignment
integer
– a 32-bit reg
Port Declaration
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input
– must be wire type
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inout
– must be wire type
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output
– can be reg or wire type
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If not specified, all of aboves are by default
wire type.
Behavioral Description
VS.
Structural Description
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Structural Description
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a Verilog description of schematic
easy to synthesize
like gate-level netlist
less readable from human’s point of view.
Behavioral Description
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a description of the functionality
flexible and more readable
suitable for large scale design
not always synthesizable
Structure Description
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primitive instantiation (AND, NAND, OR,
NOR, XOR, XNOR, BUF, NOT, BUFIF,
NOTIF)
parameter value assignment
Structural Description Example
primitive
module weird_logic (a,b,c,d);
output a;
input b,c,d;
wire w;
nand g1(w,b,c);
nor g2(a,w,d);
endmodule
don’t forget
Behavioral Description 1
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Boolean-Equation-Based Model
module weird_logic (a,b,c,d);
output a;
– continuous assignment
input b,c,d;
– level-sensitive
continuous
wire w;
assignment
assign w = ~(b & c); – normally used for
combinational circuits
assign a = ~(w | d);
endmodule
Behavioral Description 2
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Cyclic Behavior Model
module weird_logic (a,b,c,d);
–
output a;
–
input b,c,d;
reg w,a;
always@(b or c)
–
w = ~(b & c);
always@(d or posedge w)
a = ~(w | d);
endmodule
always block
can be both level
and edge sensitive
do not expire after
the last statements
Behavioral Description 2
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Cyclic Behavior Model
module weird_logic (a,b,c,d);
–
output a;
input b,c,d;
–
wire w;
always@(b or c)
–
w = ~(b & c);
always@(d or posedge w)
a = ~(w | d);
endmodule
always block
can be both level
and edge sensitive
do not expire after
the last statements
Using Testbench
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By giving a set of combination of inputs to
test the timing and functionality of your
design.
Can be separate from your design.
Must match the interface of your design
Need not to be synthesizable.
With Stimulus
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initial block
$monitor system task
$time system task
$display system task
delay statements and assignments discussion of simulator engine
$finish system task
Testbench Example
module tb_weird_logic;
wire A;
reg B, C, D;
weird_logic instance1(A, C, D, B);
initial
// two slashes introduce a single line comment
begin
$monitor ($time,,,
"A = %b B = %b C = %b D = %b", A, B, C, D);
//waveform for simulating the binaryToESeg driver
#10 B = 0; C = 0; D = 0;
#10 D = 1;
#10 C = 1; D = 0;
#10 $finish;
end
endmodule