Transcript Lecture 1: Introduction

ENEE 644
Computer-Aided Design of Digital Systems
-- Logic Synthesis and Optimization
Dr. Ankur Srivastava
Office: 1349 A.V. Williams
Email: [email protected]
URL: http://www.ece.umd.edu/class/enee644/
Course Outline
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Introduction
Algorithms and Tools
Two-Level Logic Synthesis
Multi-Level Logic Synthesis
Sequential System Synthesis
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Introduction
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Very Large Scale Integration (VLSI)
Computer-Aided Design
Design Process
Design Styles
Logic Synthesis: an Overview
Design Space and Optimization
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VLSI Circuits
 Integrated Circuits
 SSI, MSI, LSI, and VLSI
 Moore’s Law
 Microelectronics is the Enabling Technology
(Micro-Electro-Mechanics more recently)
 Design Automation is the Enabling Tool
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Moore’s Law
 The logic density of silicon integrated circuits
is doubled every 18 months.
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Intel 4004 (1971)
 Intel’s first
microprocessor
 2,300 transistors
 108 KHz
 10 micron
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Intel386™ (1985)
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First 32-bit chip
275,000 transistors
16MHz – 33 MHz
1 micron
Multi-tasking
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Pentium®III(1999)
 9.5 million transistors
 0.25-micron technology
 Internet Streaming
SIMD extensions
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Design Technology Challenges
 Productivity
design meaningfully with huge number of transistors
 Power
design under the single-chip package power limit
 Manufacturing Integration
 Interference
resource-efficient communication and synchronization
 Error-Tolerance
relaxation of the requirement of 100% correctness
Source: ITRS 2001 Edition
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Computer Aided Design
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Role
History
Difficulty: size, NP-hard
Market and Key Players
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Tens of billions $ industry
4 major CAD companies
CAD groups in large companies
Universities with strong CAD groups
 Conferences and Journals
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Brief History of CAD
 1950-1965
manual design, impractical algorithms (even for MSI).
 1965-1975
physical design tools for automatic layout of gate arrays
IBM: Engineering Design System
AT&T: LTX system for standard cells
logic design tools:
IBM’s Mini: 2-level heuristic minimizer
Espresso: (IBM and Berkeley) PLA-based design
 1975-1985
placement and routing, technology mapping, multi-level optimization
theoretical development in physical design
 1985performance/power driven design methodologies
parallel algorithm, graph theory, combinatorial optimization problems
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Design Process
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System Specification
Functional Design
Logic Design
Circuit Design
Physical Design
Fabrication
Packaging
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Design Styles
 Full Custom
 Semi-Custom
 Programmable
 Trade-off:
Cost, flexibility, performance, area, power, time-tomarket
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Logic Synthesis: Overview
 Goals:
 Generate the logic-level model of the system
 Optimize the logic-level model
 Problems and Tools:
 Two-level circuits: Boolean algebra, Binary decision
diagram
 Multi-level circuits: Boolean networks, Factored form
 Sequential circuits: Finite state machine, graph
algorithms
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Design Space and Optimality
 Implement a circuit that outputs true iff all four
inputs are true using 2- and 3-input AND gates.
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Logic specification.
How many different implementations?
Area and delay: optimization targets.
Trade-off curve and Pareto points.
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Design Space and Optimality (cont’d)
delay
optimization
failed design
delay constraint
successful design
optimal design
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Trade-off curve
Set of Pareto points
Optimal designs
infeasible design
area
area constraint
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