Transcript Delays in Verilog

Delays
in Verilog
Programmable Logic Design (40-493)
Fall 2001
Computer Engineering Department
Sharif University of Technology
Maziar Gudarzi
Introduction
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Delays are crucial in REAL simulations
Post-synthesis simulation
 Post-layout simulation
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FPGA counter-part: Post-P&R simulation
Delay Models
Represent different physical concepts
 Two most-famous models
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Inertial delay
 Transport delay
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Delay Models
Delays
in Verilog
Delay Models
Inertial Delay
The inertia of a circuit node to change
value
 Abstractly models the RC circuit seen at
the node
 Different types
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Input inertial delay
 Output inertial delay
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Delay Models
Transport Delay
Represents the propagation time of
signals from module inputs to its
outputs
 Models the internal propagation delays
of electrical elements
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Delay Types
Delays
in Verilog
Delay Types
Rise Delay
 Fall Delay
 Turn-Off Delay
 Min/Typ/Max Delay values
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Delays in
Gate-Level Modeling
Delays
in Verilog
Delays in
Gate-Level Modeling
Delay are shown by # sign in all verilog
modeling levels
 Inertial rise delay
 Inertial fall delay
 Inertial turn-off delay
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and #(rise_val, fall_val, turnoff_val) a(out,in1, in2)
Delays in
Gate-Level Modeling (cont’d)
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If no delay specified
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If only one value specified
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Default value is zero
It is used for all three delays
If two values specified
They refer respectively to rise and fall
delays
 Turn-off delay is the minimum of the two
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Delays in
Gate-Level Modeling (cont’d)
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Min/Typ/Max Values
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Another level of delay control in Verilog
Each of rise/fall/turnoff delays can have
min/typ/max values
not #(min:typ:max, min:typ:max, min:typ:max) n(out,in)
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Only one of Min/Typ/Max values can be used in
the entire simulation run
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It is specified at start of simulation, and depends to the
simulator used
Typ delay is the default
Delays in
Dataflow Modeling
Delays
in Verilog
Delays in
Dataflow Modeling
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Regular Assignment Delays
assign #delay out = in1 & in2;
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As in Gate-Level Modeling the delay is
output-inertial delay
Delays in
Dataflow Modeling (cont’d)
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Implicit Continuous Assignment Delay
wire #delay out = in1 & in2;
Delays in
Behavioral Modeling
Delays
in Verilog
Delay in
Behavioral Modeling
Today Summary
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Delays
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Models
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Inertial/Transport
Types
Rise/Fall/Turn-off
 Min/Typ/Max Values
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Delays in Verilog
Gate-Level Modeling
 Dataflow Modeling
 Behavioral Modeling
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Complementary Notes
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Assignment 6
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Chapter 8:
All 6 Exercises with ModelSim (submit the
Verilog source codes to [email protected])
 Design appropriate test-benches to
exhaustively test the results and report the
errors
 Due date: Saturday, Day 15th
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
Lab. Final Project
Announce your group members today
 Start your work
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Complementary Notes (cont’d)
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Don’t forget to subscribe to course
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