Transcript 22.Loic_lagadec-MDE.ppt

MDE based FPGA physical Design
Fast prototyping with Smalltalk
Ciprian Teodorov, Loïc Lagadec
[email protected]
Lab-STICC MOCS UMR 3192
FPGAs
“Flexible” hardware
Time to market
Compute node
Hard to program
Hard to debug
i1
LUT
LUT
I1-i2
LUT
i2
E/S
µP
LUT
LUT
i1
I1+i2
LUT
i2
LUT
LUT
LUT
Programmable
interconnection
FPGAs
“Flexible” hardware
Time to market
EDA required !
•C to circuit
•Debug
•Benchmarking
Hard to program
Hard to debug
Our Smalltalk-based EDA legacy
Legacy backfires
Early developments (MADEO) started in
1996
Fast evolving domain (Moore + Murfy)
Refactoring is not enough to keep in the
race
We have to re-design our framework
New direction
We need to shift from
a generic solution to be tailored on demand
To
a repository of model, algorithms,
components
In order to deliver
Performances
Scalability
Flexibility
Durability
LEGACY
Front end
C code
High level synthesis
(compilation)
Ressources allocation
(logic synthesis)
Circuit
Programming an FPGA in 4 steps
ADL Based EDA generators
Spécification
Architecture
Architecture
specification
ADL
Description
Exploration
Application
Synthesizer
Compiler P&R
Compilation
Synthesis/Compilation
HW
Bitstream HW
generator Prototype Prototype
Simulation
Configuration
Testbenches Testbenches
Controller
Simulation
Validation Validation
10
Our flow
Context
Resources
ADL
Description
Zone
Zone
Zone
Reconfigurable
zones
description
Behavioral
code
Bitstream
model
Bistream
Resource
model
Architecture
VHDL
Configuration
model
Configuration
controller
Prototype
Simulation & synthesis
11
Some examples
12
RE-DESIGN
Goal oriented view extraction
Tool engine
Models as common vocabulary
Combinational circuit modeling
Target modeling
Re-design / copy down
CONCLUSION
Let’s try to summarize
Succes: target, tool flow
Conclusion
Future work:
Tools integration (eg Mondrian integration)
Performances improvement
Test coverage
Algorithm pick and play GUI
Thank you for your attention