Transcript slides
Review for Exam 1
Chapters 1 through 3
CSE260-1-1
Chapter 1 Overview
Information Representation
Number Systems [binary, octal and
hexadecimal]
Base Conversion
Decimal Codes [BCD (binary coded
decimal)]
Alphanumeric Codes
Parity Bit
Gray Codes
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1-2 Number Systems
Positive radix, positional number systems
Examples:
• Decimal (radix r =10)
Ex: 24.3 = 2x101 + 4x100+3x10-1
• Binary (radix r =2)
Digits (0-9)
Ex: 1101.01 = ( . )10
• Octal (radix r = )
• Hexadecimal (r =
Bits (0-1)
)
Digits: 1,2,…9, A, B, C, D, E, F
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Range of numbers
Binary number: ex. a 3-bit number: n=3
• 000, 001 … ,111
or in decimal system: 0, 1 … 7
Total of 8 numbers (=23)
Range: from 0 to 7 (0 to 23-1)
• In general a n-bit number represents:
2n different numbers
Min: 0
Max number: 2n-1
For fractions: m bits after the radix point:
• Min: 0
• Max number:
(2m -1)/2m
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Use of HEX system
Short hand notation of large binary numbers:
• Each HEX digits can be represented by exactly 4 bits
•
(16=24)
Thus (10011110.0101)2
9
E .
5
Conversion from binary to HEX and HEX to binary is
very easy:
(10011101)2 = (
)16
(1010110110.11)2 = (
B39.716 = (
)2
)16
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Octal system
Radix r = 8
8 digits:
• 0, 1, 2,…7
Ex: 2758 = 2x82 + 7x8 + 5x1 = 128 + 56 + 5
= 18910
Each octal digit can be represented by 3 bits
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1-3 Conversion Between Bases
To convert from one base to another:
1) Convert the Integer Part
2) Convert the Fraction Part
3) Join the two results with a radix point
CSE260-1-7
Example: convert (325.65)10 to hex
Integer part: 32510 = (
325/16 = 20 and rem = 5
20/16 = 1 and rem = 4
1/16 = 0 and rem = 1
Fractional part: .65
. )16
Least significant digit
Most significant
Thus 32510 = 14516
0.65x16 = 10.4 thus int = 10= A Most significant
0.4x16 = 6.4 thus int = 6
0.4x16 = 6.4 thus int = 6
Least significant
Etc.
Thus .6510 = A6616
325.6510 = 145.A6616
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Conversion - Summary
Divisions (or x) by 16
Ai.16i
Decimal
SAi.2i
Binary
Ai.8i
Group in
bits of 3
Hexadecimal
Group in
bits of 4
Octal Hex:
through the binary
representation
Octal
CSE260-1-9
1-4 Binary Codes
A n-bit binary code is a n-bit word
which can represent up to 2n
different elements.
Example: 3-bit code can represent
up to 8 different elements”
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Binary Coded Decimal (BCD)
The BCD code is the 8,4,2,1 code.
This code only encodes the first ten
values from 0 to 9.
Each decimal digit is coded
separately by 4 bits
Example:
• (325)10 = (0011 0010 0101)BCD
3
2
Exercise: (856)10 = (
5
)BCD
CSE260-1-11
Overview Chapter 2
•
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•
•
•
•
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Binary Logic and Gates
Boolean Algebra
Standard Forms
Two-Level Optimization
Map Manipulation
Other Gate Types
Exclusive-OR Operator and Gates
High-Impedance Outputs
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Operator Definitions and Truth
Tables
Truth table - a tabular listing of the values of a
function for all possible combinations of values
on its arguments
Example: Truth tables for the basic logic
operations:
X
0
0
1
1
AND
Y Z = X·Y
0
0
1
0
0
0
1
1
X
0
0
1
1
Y
0
1
0
1
OR
Z = X+Y
0
1
1
1
NOT
X
0
1
Z=X
1
0
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2-2 Boolean Algebra
Boolean algebra deals with binary variables and
a set of three basic logic operations: AND (.), OR
(+) and NOT ( ) that satisfy basic identities
Basic identities
1.
3.
5.
7.
9.
X + 0= X
X+ 1=1
X + X= X
X + X=1
X = X Involution
2.
4.
6.
8.
X. 1=X
X . 0=0
X .X =X
X .X =0
Dual
Existence 0 and 1 or
operations with 0 and 1
Idempotence
Existence complements
Replace “+” by “.”, “.” by +,
“0” by “1” and “1’’ by”0”
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Boolean Algebra
Boolean Theorems of multiple variables
10. X + Y =Y + X
14. X (Y+Z) = XY+XZ
11. XY =YX
13. (XY)Z =X(YZ )
Associative
Distributive 15. X+ YZ = (X + Y)(X + Z)
16. X + Y = X . Y
DeMorgan’s
12. (X + Y) + Z = X + (Y+ Z)
Commutative
17. X . Y = X + Y
Dual
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Other useful Theorems
Dual
(X + Y)(X + Y) = Y
XY + XY = Y
Minimization
X + XY = X
Absorption
X(X + Y) = X
X + XY = X + Y
Simplification
X(X + Y) = XY
XY + XZ + YZ = XY + XZ
Consensus
(X + Y)( X + Z)(Y + Z) = (X + Y)( X + Z)
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2-3 Standard (Canonical) Forms
It is useful to specify Boolean
functions in a form that:
• Allows comparison for equality.
• Has a correspondence to the truth
tables
Canonical Forms in common usage:
• Sum of Products (SOP), also called Sum
or Minterms (SOM)
• Product of Sum (POS), also called
Product of Maxterms (POM)
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Maxterms and Minterms
Examples: Two variable minterms and
maxterms.
Index
Minterm
Maxterm
0 (00)
xy
x+y
1 (01)
xy
x+y
2 (10)
xy
x+y
3 (11)
xy
x+y
The index above is important for describing
which variables in the terms are true and which
are complemented.
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Index Examples – Four Variables
Minterm Maxterm
mi
Mi
abcd a b c d
?
abcd
?
abcd
abcd a b c d
?
abcd
abcd a b c d
?
abcd
abcd a b c d
Notice: the variables
are in alphabetical
order in a standard
form
Index Binary
i Pattern
0
0000
1
0001
3
0011
5
0101
7
0111
10
1010
13
1101
15
1111
Relationship between min and MAX term?
M i = mi
mi = M i
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Minterm Function Example
F(A, B, C, D, E) = m2 + m9 + m17 + m23
F(A, B, C, D, E) write in standard form:
A’B’C’DE’ + A’BC’D’E + AB’C’D’E + AB’CDE
m2
m9
m17
m23
Sum of Product (SOP) expression:
• F = Σm(2, 9, 17, 23)
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Expressing a function with
Maxterms
Start with the SOP: F1(x,y,z) =m1 + m4 + m7
Thus its complement F1can be written as
• F1 = m0 +m2 +m3 + m5 + m6 (missing term of F1)
Apply deMorgan’s theorem on F1:
• (F1 = (m0 +m2 +m3 + m5 + m6)
= m0.m2.m3.m5.m6
= M0.M2.M3.M5.M6
also called, Big M notation
= ΠM(0,2,3,5,6)
Thus the Product of Sum terms (POS):
F1 = (x + y + z) ·(x + y + z)·(x+ y + z)
·(x + y + z)·(x + y + z)
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2-4 Circuit Optimization
Goal: To obtain the simplest
implementation for a given function
Optimization requires a cost criterion to
measure the simplicity of a circuit
Distinct cost criteria we will use:
• Literal cost (L)
• Gate input cost (G)
• Gate input cost with NOTs (GN)
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Literal Cost
Literal – a variable or its complement
Literal cost – the number of literal
appearances in a Boolean expression
corresponding to the logic circuit
diagram
Examples (all the same function):
•
•
•
•
F = BD + AB’C + AC’D’
F = BD + AB’C + AB’D’ + ABC’
F = (A + B)(A + D)(B + C + D’)( B’ + C’ + D)
Which solution is best?
L=8
L=
L=
23
Karnaugh Maps (K-map)
A K-map is a collection of squares
• Each square represents a minterm
• The collection of squares is a graphical representation
•
•
of a Boolean function
Adjacent squares differ in the value of one variable
Alternative algebraic expressions for the same function
are derived by recognizing patterns of squares
The K-map can be viewed as
• A reorganized version of the truth table
• A topologically-warped Venn diagram as used to
visualize sets in algebra of sets
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2-5 Map Manipulation:
Systematic Simplification
A Prime Implicant is a product term obtained by
combining the maximum possible number of adjacent
squares in the map into a rectangle with the number of
squares a power of 2.
A prime implicant is called an Essential Prime Implicant
if it is the only prime implicant that covers (includes)
one or more minterms.
Prime Implicants and Essential Prime Implicants can be
determined by inspection of a K-Map.
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Don't Cares in K-Maps
Sometimes a function table or map contains entries
for which it is known:
• the input values for the minterm will never occur, or
• The output value for the minterm is not used
In these cases, the output value need not be defined
Instead, the output value is defined as a “don't care”
By placing “don't cares” ( an “x” entry) in the function
table or map, the cost of the logic circuit may be
lowered.
Example 1: A logic function having the binary codes
for the BCD digits as its inputs. Only the codes for 0
through 9 are used. The six codes, 1010 through 1111
never occur, so the output values for these codes are
“x” to represent “don’t cares.”
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Other Gate Types: overview
A
A
B
A
B
NAND
NOR
A
B
A
B
A B
BUF
XOR XNOR
0 0
0
1
1
0
1
0 1
1 0
0
1
1
1
0
0
1
1
0
0
1 1
1
0
0
0
1
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The Tri-State Buffer
Symbol
IN
OUT
EN
Truth Table
EN
0
1
1
IN
X
0
1
OUT
Hi-Z
0
1
For the symbol and truth table,
IN is the data input, and EN,
the control input.
For EN = 0, regardless of the
value on IN (denoted by X),
the output value is Hi-Z.
For EN = 1, the output value
follows the input value.
Variations:
• Data input, IN, can be inverted
• Control input, EN, can be inverted
by addition of “bubbles” to signals.
OUT= IN.EN
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Logic and Computer Design Fundamentals
Chapter 3 – Combinational
Logic Design
Charles Kime & Thomas Kaminski
© 2008 Pearson Education, Inc.
(Hyperlinks are active in View Show mode)
NAND Mapping Algorithm
1. Replace ANDs and ORs:
.
.
.
.
.
.
.
.
.
.
.
.
2. Repeat the following pair of actions until there
is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
.
.
.
.
.
.
NOR Mapping Algorithm
1. Replace ANDs and ORs:
.
.
.
.
.
.
.
.
.
.
.
.
2. Repeat the following pair of actions until there
is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
.
.
.
.
.
.
Enabling Function
Enabling permits an input signal to pass
through to an output
Disabling blocks an input signal from passing
through to an output, replacing it with a fixed
value
The value on the output when it is disable can
be Hi-Z (as for three-state buffers and
transmission gates), 0 , or 1 ENX
F
When disabled, 0 output
When disabled, 1 output
See Enabling App in text
(a)
X
F
EN
(b)
3-7 Decoding
A n-bit binary code can represent up to m=2n
elements:
encoding
m elements
n-bit binary code
(ex. 256 alpha-num. chars) decoding
(ex. 8-bit ASCII code)
Decoding - the conversion of an n-bit input code
to an m-bit output code with
n ≤ m ≤ 2n such that each valid code word
produces a unique output code
n bits
A0
:
:
An-1
n-2n
decoder
D0
D1
:
:
Dm-1
m-elements
≤ 2n
2-to-4 Line Decoder circuit
A0
A1
D0 = A1 A0
D1 = A1 A0
D2 = A1 A0
D3 = A1 A0
Notice that the outputs of the decoder
correspond to the minterms: Di=mi
Decoder Expansion
Larger decoders can be realized by
implementing each minterm using a single
AND gate:
• However for large decoders this requires
multiple input AND gates which is not always
feasible.
• Better to use a hierarchical approach: build
larger ones from smaller decoders.
Approach:
• Output AND gates have only 2 inputs and
implement the minterms.
• The output AND gates are driven by two
decoders with their numbers of inputs either
equal or differing by 1.
Rule for building large decoders
k-to-2k decoder:
• One needs 2k output AND gates
• If k can be divided by 2:
use two k/2-to-2k/2 decoders
• If k cannot divided by 2:
use a (k+1)/2 and
use a (k-1)/2 decoder.
Previous example: 3-to-8 decoder
(k=3):
• Use a 2-to-4 and a 1-to-2 decoder
Combinational Logic Implementation
- Decoder and OR Gates
Implement m functions of n variables
with:
• Sum-of-minterms expressions
• One n-to-2n-line decoder
• m OR gates, one for each output
Example
Design and implement a majority
function F(ABC) using a 3-to-8
decoder
Indicate MSB, LSB
ABC F
000 0
Truth table:
0
Minterms:
• F=Sm(3,5,6,7)
001
010
011
100
101
110
111
0
0
1
0
1
1
1
A
2
B
1
C
0
1
2
3
4
5
6
7
Implementation using decoder:
F
Encoding
Typically, an encoder converts a code
containing exactly one bit that is 1 to a binary
code corresponding to the position in which the
1 appears: ex. D1=1 output 0001
D0
D1
:
:
Dm-1
0
1
2
3
m-1
0
encoder
0
1
0
0
0
1
2
n-1
A0
:
:
An-1
1
0
0
0
Examples: Octal-to-Binary encoder
Other examples?
Priority Encoder
D0
0
1
D1
1
D2
2
?
0
D3
A1
A0
3
V
To
processor
If more than one input value is 1, then the encoder
just designed does not work.
An encoder that can accept all possible
combinations of input values and produce a
meaningful result is a priority encoder.
Among the 1s that appear, it selects the most
significant input position (or the least significant
input position) containing a 1 and responds with
the corresponding binary code for that position.
3-9 Selecting (multiplexers)
Selecting of data or information is a critical
function in digital systems and computers
Circuits that perform selecting have:
• A set of n information inputs from which the selection is
made
• A set of k control (select) lines for making the selection
I0
• A single output
0
n ≤ 2k inputs
I1
I2
I3
1
2
3
:
:
In-1
n-1
OUT
k-1 .. 1 0
Sk-1..S1 S0
k select lines
4:1 MUX realization
Expression for OUT
OUT = S1S0 I0+ S1S0 I1+ S1S0 I2+ S1S0 I3
m0
m1
m2
m3
S1 S0 OUT
0 0
I0
0 1
I1
1 0
I2
1 1
I3
2k-1
or OUT = Σ mi Ii
i=0
Circuit implementation: SOP
• 4 AND gates (4 product terms)
• 2-to-4 line decoder (to generate the
minterms)
Exercise
Build a 8:1 MUX using two 4:1 and one 2:1 muxes
I0
I1
I2
I3
I4
I5
I6
I7
0
1
2 4:1
3
1 0
0
S1
1
S0
0
1
2 4:1
3
1 0
S1
S0
OUT
S2
Ex: S2S1S0=110 : select I6
Multiplexer-based combinational circuits
realization- Approach 1
A mux can be easily used to implement a
function defined by a truth table (lookup table)
Indeed the output F of a mux is equal to:
2k-1
F = Σ mi Ii
Example
i=0
Give the input Ii the
value of 0 or 1
as shown in the truth table
0
1
1
0
0
1
2 4:1
3
1 0
A
B
F
A
0
0
1
1
B OUT =F
0
I0
0 m0
1
I1
1 m1
0
I2
1 m2
1
I3
0 m3
F= Σm(1,2)
Combinational Logic Implementation
- Multiplexer Approach 2
Implement any m functions of n + 1
variables by using:
• An m-wide 2n-to-1-line multiplexer
Design:
• Find the truth table for the functions.
• Based on the values of the first n variables,
separate the truth table rows into pairs
• For each pair and output, define a rudimentary
function of the final variable (0, 1, X, X )