Transcript PowerPoint file

Microprocessor System Design
Omid Fatemi
Memory Interfacing
([email protected])
University of Tehran 1
Outline
• Address decoding
• Chip select
• Memory configurations
University of Tehran 2
Processor Timing Diagram of 8088 (Minimum Mode)
for Memory or I/O Read (with 74245)
T1
T2
T3
T4
CLOCK
__
DT/R
ALE
D7 - D0
D7 - D0 (from memory)
from memory to 74LS245
AD7 - AD0
A7 - A0
A15 - A8
A19/S6 - A16/S3
A19 - A0
from 74LS373 to memory
garbage
D7 - D0 from
74LS245
A15 - A8
A19 - A16
S6 - S3
A19 - A0 from 74LS373
__
IO/M
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
____
RD
______
DEN
University of Tehran 3
Minimum Mode
A7 - A0
DEN
DT / R
E
DIR
AD7 - AD0
A15 - A8
A19/S6 - A16/
S3
RD
OE
LE
A7 - A0
A15 - A8
A19 - A16
Q7 - Q0
MEMORY
74LS373
D7 - D4
D3 - D0
GND
ALE
OE
LE
Q7 - Q0
74LS373
D7 - D0
GND
8088
OE
LE
D7 - D0
74LS245
D7 - D0
GND
B7 - B0
Q7 - Q4
Q3 - Q0
74LS373
RD
IO / M
WR
WR
University of Tehran 4
Minimum Mode
D7 - D0
D7 - D0
A19 - A0
A19 - A0
Simplified
Drawing of
8088 Minimum
Mode
MEMORY
MEMR
RD
MEMW
WR
When Memory is selected?
University of Tehran 5
Minimum Mode
220 bytes or 1MB
D7 - D0
D7 - D0
A19 - A0
A19 - A0
Simplified
Drawing of
8088 Minimum
Mode
MEMORY
MEMR
RD
MEMW
WR
CS
University of Tehran 6
What are the memory locations of a
1MB (220 bytes) Memory?
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
Example: 34FD0
0011 0100 11111 1101 0000
University of Tehran 7
Interfacing a 1MB Memory to the 8088 Microprocessor
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
SS
DS
ES
XXXX
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
DI
XXXX
XXXX
IP
XXXX
FFFFF
FFFFE
FFFFD
A19
:
A0
A19
:
A0
D7
:
D0
D7
:
D0
MEMR
RD
MEMW
WR
CS
:
:
20023
20022
20021
20020
:
:
10008
10007
10006
10005
10004
10003
10002
10001
10000
:
:
00001
00000
36
25
19
:
:
13
7D
12
29
:
:
8A
F4
07
88
42
39
27
98
45
:
:
95
23
University of Tehran 8
Instead of Interfacing 1MB, what will happen if
you interface a 512KB Memory?
University of Tehran 9
What are the memory locations of a
512KB (219 bytes) Memory?
A18 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
University of Tehran 10
Interfacing a 512KB Memory to the 8088 Microprocessor
AX
BX
CX
3F1C
0023
0000
DX
FCA1
A19
A18
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
:
A0
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
What do we do with A19?
A18
7FFFF
36
:
A0
7FFFE
7FFFD
25
19
D7
D7
:
:
:
D0
:
D0
MEMR
RD
MEMW
WR
CS
20023
20022
20021
20020
:
:
:
:
13
7D
12
29
:
:
00001
95
00000
23
University of Tehran 11
What if you want to read physical address A0023?
AX
BX
CX
3F1C
0023
0000
DX
FCA1
A19
A18
CS
XXXX
SS
DS
ES
XXXX
A000
XXXX
:
A0
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A18
7FFFF
36
:
A0
7FFFE
7FFFD
25
19
D7
D7
:
:
:
D0
:
D0
MEMR
RD
MEMW
WR
CS
20023
20022
20021
20020
:
:
:
:
13
7D
12
29
:
:
00001
95
00000
23
University of Tehran 12
What if you want to read physical
address A0023?
A19 to
A0
(HEX)
A0023
AAAA
1111
9876
1010
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
0010
0011
A19 is not connected to the memory so
even if the 8088 microprocessor
outputs a logic “1”, the memory
cannot “see” this.
University of Tehran 13
What if you want to read physical
address 20023?
A18 to
A0
(HEX)
20023
AAAA
1111
9876
0010
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
0010
0011
For memory it is the same as previous
one.
University of Tehran 14
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
BX
CX
DX
3F1C
0023
0000
FCA1
CS
SS
DS
ES
XXXX
XXXX
2000
XXXX
BP
SP
XXXX
XXXX
SI
DI
XXXX
XXXX
IP
XXXX
A19
A18
:
A0
A18
:
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
CS
A18
:
A0
D7
:
D0
RD
WR
CS
7FFFF
7FFFE
7FFFD
:
20023
20022
20021
20020
:
00001
00000
36
25
19
:
13
7D
12
29
:
95
23
7FFFF
7FFFE
7FFFD
:
20023
20022
20021
20020
:
00001
00000
12
98
2C
:
33
45
92
A3
:
D4
97
University of Tehran 15
Interfacing two 512KB Memory to the 8088 Microprocessor
• Problem: Bus Conflict. The two memory
chips will provide data at the same time when
microprocessor performs a memory read.
• Solution: Use address line A19 as an
“arbiter”. If A19 outputs a logic “1” the upper
memory is enabled (and the lower memory is
disabled) and vice-versa.
University of Tehran 16
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
3F1C
A19
BX
0023
A18
CX
0000
:
DX
FCA1
A0
A0
D7
D7
CS
XXXX
SS
XXXX
DS
2000
ES
XXXX
BP
XXXX
SP
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
:
7FFFF
36
A18
7FFFE
25
:
7FFFD
19
:
:
20023
13
20022
7D
20021
12
20020
29
:
D0
D0
MEMR
RD
:
:
MEMW
WR
00001
95
CS
00000
23
7FFFF
12
A18
7FFFE
98
:
7FFFD
2C
:
:
20023
33
20022
45
20021
92
20020
A3
RD
:
:
WR
00001
D4
CS
00000
97
A0
D7
:
D0
University of Tehran 17
What are the memory locations of two
consecutive 512KB (219 bytes) Memory?
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
80000
1000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
University of Tehran 18
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
BX
CX
3F1C
0023
0000
A19
A18
:
7FFFF
7FFFE
7FFFD
36
25
19
DX
FCA1
A0
A0
:
20023
20022
:
13
7D
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
D7
:
D0
D7
:
D0
RD
WR
20021
20020
:
00001
12
29
:
95
MEMR
MEMW
BP
SP
XXXX
XXXX
CS
00000
23
SI
XXXX
7FFFF
12
DI
XXXX
7FFFE
7FFFD
:
20023
98
2C
:
33
IP
XXXX
RD
20022
20021
20020
:
45
92
A3
:
WR
CS
00001
00000
D4
97
A18
:
When the P outputs
an address between
80000 to 7FFFF,
00000
FFFFF,
this memory is
selected
A18
:
A0
D7
:
D0
University of Tehran 19
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
BX
3F1C
0023
A19
A18
A18
7FFFF
7FFFE
36
25
CX
DX
0000
FCA1
:
A0
:
A0
7FFFD
:
19
:
D7
:
D7
:
20023
20022
13
7D
CS
XXXX
SS
DS
XXXX
2000
D0
D0
20021
20020
12
29
ES
XXXX
MEMR
RD
:
MEMW
WR
CS
00001
00000
95
23
12
98
:
BP
XXXX
SP
XXXX
SI
DI
XXXX
XXXX
A18
7FFFF
7FFFE
XXXX
:
A0
7FFFD
:
2C
:
20023
20022
33
45
20021
92
RD
20020
:
A3
:
WR
CS
00001
00000
D4
97
IP
D7
:
D0
University of Tehran 20
Interfacing two 512KB Memory to the 8088 Microprocessor
AX
BX
3F1C
0023
A19
A18
A19
A18
A18
7FFFF
7FFFE
36
25
CX
DX
0000
FCA1
:
A0
:
A0
:
A0
7FFFD
:
19
:
D7
:
D7
:
D7
:
20023
20022
13
7D
CS
XXXX
SS
DS
XXXX
2000
D0
D0
D0
20021
20020
12
29
ES
XXXX
MEMR
RD
RD
:
MEMW
WR
WR
CS
00001
00000
95
23
12
98
:
BP
XXXX
SP
XXXX
SI
DI
XXXX
XXXX
A18
7FFFF
7FFFE
XXXX
:
A0
7FFFD
:
2C
:
20023
20022
33
45
20021
92
RD
20020
:
A3
:
WR
CS
00001
00000
D4
97
IP
D7
:
D0
University of Tehran 21
What if we remove the lower memory?
AX
BX
CX
3F1C
0023
0000
A19
A18
:
7FFFF
7FFFE
7FFFD
36
25
19
DX
FCA1
A0
A0
:
20023
20022
:
13
7D
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
D7
:
D0
D7
:
D0
RD
WR
20021
20020
:
00001
12
29
:
95
MEMR
MEMW
BP
SP
XXXX
XXXX
CS
00000
23
SI
XXXX
7FFFF
12
DI
XXXX
7FFFE
7FFFD
:
20023
98
2C
:
33
IP
XXXX
RD
20022
20021
20020
:
45
92
A3
:
WR
CS
00001
00000
D4
97
A18
:
A18
:
A0
D7
:
D0
University of Tehran 22
What if we remove the lower memory?
AX
BX
CX
3F1C
0023
0000
A19
A18
:
7FFFF
7FFFE
7FFFD
36
25
19
DX
FCA1
A0
A0
:
20023
20022
:
13
7D
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
D7
:
D0
D7
:
D0
RD
WR
20021
20020
:
00001
12
29
:
95
MEMR
MEMW
BP
SP
XXXX
XXXX
CS
00000
23
SI
XXXX
DI
XXXX
IP
XXXX
A18
:
When the P outputs
an address between
80000 to 7FFFF,
00000
FFFFF, no
this memory
memory
chipisis
selected
!
University of Tehran 23
Full and Partial Decoding
• Full Decoding
– When all of the “useful” address lines are connected the
memory/device to perform selection
• Partial Decoding
– When some of the “useful” address lines are connected
the memory/device to perform selection
– Using this type of decoding results into roll-over
addresses
University of Tehran 24
Full Decoding
AX
BX
CX
3F1C
0023
0000
A19
A18
:
7FFFF
7FFFE
7FFFD
36
25
19
DX
FCA1
A0
A0
:
20023
20022
:
13
7D
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
D7
:
D0
D7
:
D0
RD
WR
20021
20020
:
00001
12
29
:
95
MEMR
MEMW
BP
SP
XXXX
XXXX
CS
00000
23
SI
XXXX
DI
XXXX
IP
XXXX
A18
:
University of Tehran 25
Full Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
80000
AAAA
1111
9876
1000
0000
0000
FFFFF
1111
1111
1111
1111
1111
A19 should be a logic “1” for the
memory chip to be enabled
University of Tehran 26
Full Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
Therefore if the microprocessor
outputs an address between 00000 to
7FFFF, whose A19 is a logic “0”, the
memory chip will not be selected
University of Tehran 27
Partial Decoding
AX
BX
CX
3F1C
0023
0000
DX
FCA1
A19
A18
CS
XXXX
SS
DS
ES
XXXX
2000
XXXX
:
A0
BP
SP
XXXX
XXXX
SI
XXXX
DI
XXXX
IP
XXXX
A18
7FFFF
36
:
A0
7FFFE
7FFFD
25
19
D7
D7
:
:
:
D0
:
D0
MEMR
RD
MEMW
WR
CS
20023
20022
20021
20020
:
:
:
:
13
7D
12
29
:
:
00001
95
00000
23
University of Tehran 28
Partial Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
80000
1000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
The value of A19 is INSIGNIFICANT to the
memory chip, therefore A19 has no bearing
Universityor
of Tehran
whether the memory chip will be enabled
not 29
Partial Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
80000
1000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
ACTUAL ADDRESS
University of Tehran 30
Partial Decoding
A19 to
A0
(HEX)
AAAA
1111
5432
0000
AAAA
1198
1000
0000
AAAA
7654
AAAA
3210
00000
AAAA
1111
9876
0000
0000
0000
7FFFF
0111
1111
1111
1111
1111
80000
1000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
ACTUAL ADDRESS
University of Tehran 31
Interfacing two 512K Memory Chips to
the 8088 Microprocessor
A19
A18
:
A18
:
A0
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
8088
Minimum
Mode
512KB
#2
CS
A18
:
A0
D7
:
512KB
#1
D0
RD
WR
CS
University of Tehran 32
Interfacing one 512K Memory Chips to
the 8088 Microprocessor
A19
A18
:
A18
:
A0
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
8088
Minimum
Mode
512KB
CS
University of Tehran 33
Interfacing one 512K Memory Chips to
the 8088 Microprocessor (version 2)
A19
A18
:
A18
:
A0
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
8088
Minimum
Mode
512KB
CS
University of Tehran 34
Interfacing one 512K Memory Chips to
the 8088 Microprocessor (version 3)
A19
A18
:
A18
:
A0
A0
D7
:
D0
D7
:
D0
MEMR
MEMW
RD
WR
8088
Minimum
Mode
512KB
CS
University of Tehran 35
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#1
University
CS
of Tehran 36
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#1
University
CS
of Tehran 37
Memory chip#__ is mapped to:
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
-----
----
----
----
----
----
-----
----
----
----
----
----
University of Tehran 38
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#1
University
CS
of Tehran 39
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
CS
256KB
#1
University of Tehran 40
Interfacing four 256K Memory
Chips to
the 8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
I1
I0
O3
A17
CS
A17
:
:
A0
D7
A0
D7
:
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
D0
RD
WR
O2
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
O1
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
O0
CS
256KB
#1
University of Tehran 41
A12
:
Interfacing several
8K Memory Chips to
the 8088 P
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#?
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
University of Tehran 42
A12
:
Interfacing 128
8K Memory Chips to
the 8088 P
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#128
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
University of Tehran 43
A12
:
Interfacing 128
8K Memory Chips to
the 8088 P
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#128
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
University of Tehran 44
Memory chip#__ is mapped to:
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
-----
----
----
----
----
----
-----
----
----
----
----
----
University of Tehran 45
Memory Terms
• Capacity
– Kbit, Mbit, Gbit
• Organization
– Address lines
– Data lines
• Speed / Timing
– Access time
• Write ability
– ROM
– RAM
University of Tehran 46
ROM Variations
• Mask Rom
• PROM – OTP
• EPROM – UV_EPROM
• EEPROM
• Flash memory
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RAM Variations
• SRAM
• DRAM
• NV-RAM
– SRAM – CMOS
– Internal lithium battery
– Control circuitry to monitor Vcc
University of Tehran 48
Memory Chip
• 8K SRAM
• to be specific:
– 8Kx8 bits SRAM
A0
A1
I/O0
I/O1
A2
I/O2
A3
I/O3
A4
A5
A6
I/O4
I/O5
I/O6
A7
I/O7
A8
A9
A10
6264
A11
A12
OE
WE
CS1
CS2
University of Tehran 49
6264 Block Diagram
University of Tehran 50
6264 Function Table
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Memory Chip
• 8K EPROM
• to be specific:
– 8Kx8 bits EPROM
A0
A1
Q0
Q1
A2
Q2
A3
Q3
A4
A5
A6
Q4
Q5
Q6
A7
Q7
A8
A9
A10
2764
A11
A12
G
P
C
VPP
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2764 Block Diagram
Chip enable
Output enable
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Operating Modes
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Programming 2764
• after each erasure for UV-EPROM):
– all bits of the M2764A are in the “1" state.
• The only way to change a “0" to a ”1" is by
ultraviolet light erasure.
• Programming mode when:
– VPP input is at 12.5V
– E and P are at TTL low.
• The data to the data output pins.
• The levels required for the address and data
inputs are TTL.
University of Tehran 55
A12
:
Interfacing 128
8K Memory Chips to
the 8088 P
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#128
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
University of Tehran 56