Transcript Discrete trap이 mobility 및 channel의 current flux에 미치는 영향을

Trap Engineering for device design and reliability
modeling
in memory/logic application
2015년 02월 xx일
대표 학생
이승만
과제 책임자
박영준 교수
School of EE,
Seoul National University
1/12
4.5년간 전략산학 연구 성과 결산
연구 성과 요약 (’10.07~’14. 12)
1. 참여 기간 : 2010. 07. 01 ~ 현재
2. 전략산학 장학생 현황 : (총 0 명)
- 1차년도 이후 누적 입사 : 총 4명 (입사: 우준명, 박수영, 심경석, 최연규)
- 학술연수: 총 8명 (졸업: 이석하, 권혁제, 박상용, 권주성, 심혜원 / 김희중, 문중수, 김강욱)
3. 대표 연구 주제 :
- 3D MCRD framework을 통한 NBTI-SILC-TDDB simulation
- BEOL TDDB 에 대한 Theoretical approach (MC / analytic method)
- Billions of transistors에 대한 소자 산포 예측, tail part modeling
2/12
대표 논문 Review
논문 제목 :
A 3-D Statistical Simulation Study of Mobility
Fluctuations in MOSFET Induced by Discrete
Trapped Charges in SiO2 Layer
논문 내용 :
- Discrete trap이 mobility 및 channel의 current flux에 미치
는 영향을 분석하였다. Si bar에 대한 atomistic한 시뮬레이션
을 통해 트랩 주변으로 흐르는 current contour가 mobility
degradation에 직접적인 영향을 준다는 것을 보였다.
3/12
대표 논문 Review
선정 이유 :
- Discrete trap이 mobility 및 channel의 current flux에 미치는 영향을
분석하였음. 이러한 현상은 scale down된 소자의 trap에 의한 신뢰성 분석
에 필수적이며 본 연구 과제의 주된 방법론임.
저널 정보 :
-
저널명 : IEEE Transactions on Nanotechnology
-
IF: 1.619, SJR 6175/29385
-
Published 4 SCI Journal papers, 13 conference papers
4/12
Introduction
Status/Steps : Development of 3D MCRD Simulation Framework
1) Achievements: Unified Oxide Reliability Modeling Framework
 Interface reaction
 Molecular transport: Brownian random motion
 Conversion from precursor to active trap
 Leakage: Trap Assisted Tunneling current
 Breakdown: percolation model
 Based on stochastic MC particle simulation
- Solving present issues of ‘Causes’ and ‘Effects’ of degradation



NBTI relaxation
Unified model of NBTI-SILC-TDDB
BEOL oxide TDDB
 Setting up for practical simulation Framework
2) Predicting ‘tail’ part of 1 Billion transistors regarding step 1).
 percolation approach
 Oxide trap + discrete dopant
 dVt distribution of 1Billion transistors in tractable time
and resources
5
-> Trajectory of sample
hydrogen in the oxide
Unified Model of NBTI-SILC-TDDB in Gate Oxide
Modeling Strategy
cause
[NBTI: Negative Bias
Temperature Instability]
3
BEOL oxide TDDB
•
1.0
3x10
(a)
0.9
(b)
0.8
3
10
•
0.25
t
0.5
13
-2
0.4
13
-2
0.3
12
-2
12
-2
Dit0=5.00×10 cm
2
10
0.6
Dit0=1.25×10 cm
•
•
0.2
Dit0=5.56×10 cm
Dit0=3.13×10 cm
Nit / Nit(tr=0)
Nit (#)
0.7
without diffusion
(well-based model
w/ small dispersion)
decrease Dit0
c=3.5
0.1
Å
RD model (1D)
-3
10
-2
10
-1
10
0
10
time (s)
1
10 10-3 10-2 10-1 100 101 102
0.0
Apply percolation theory with MC
method
Field dependence based on
percolation model
Statistical Analysis
Development of Analytical model
time (s)
Oxide Trap Profile
> Gbit cells?
effects
[SILC: Stress Induced
Leakage Current]
[TDDB: Time Dependent
Dielectric Breakdown]
10-6
200 devices
Ig (a.u.)
10-7
10-8
L/W=40nm/40nm
tox=6nm
10-9
10-10
1.3x10-2
10-1
100
101
time (s)
6
Statistical approach to the reliability
Need to predict..
-
VT ,∆VT distribution before/after stress(NBTI)
6𝜎 tail (6𝜎 ∶ 99.9999998% , 1/109)
What makes the tail part of the distribution? What is the worst case?
PDF
PDF
VT
Time 0
- Random Dopant
VT
After aging(NBTI,)
- Trap(E,r)
“Anomalously” ∆𝑉𝑇 140mV, “average” 40mV - A. Brown, TED VOL.57,NO.9, Sep.
2010
Goal for statistical analysis
-
Predicting the probability and ∆𝑉𝑇 of the worst case (S/D current of the MOS device
is blocked by the potential chain formed by oxide traps and substrate dopants.)
Finding rule for WC
 V T _ total   VT _ LER 2   VT _ MGG 2   VT _ RDF 2   VT _ RTD 2  ..
 V T _ total  F ( VT _ LER ,  VT _ MGG ,  VT _ RDF ,  VT _ RTD ,..)
  V T _ total  F ( VT _ LER ,  VT _ MGG ,  VT _ RDF ,  VT _ RTD ,..,  VT _ Potential _ Mountains )
3/12
Verifying physical validity
Probability of the WC
Worst case analysis (current blocking potential mountain chain)
Identifying anomalous VT shift according to the trap(fixed charge) distribution
uniformly
Type
L
randomly
Vertically distributed
W Tox(SiO2) N-Sub(ND)
PMOS 50nm 40nm
2nm
20 fixed charges
– 1e12/cm2
5e18/cm3
40 fixed charges
- 2e12/cm2
80 fixed charges
- 4e12/cm2
VD = -0.05V
|Id|[I]
1E-6
1E-7
1E-8
1E-9
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
|VG|[V]
7/12
4
0
Density of Fixed Charges(/cm2)
12
12
1x10
12
2x10
12
3x10
4x10
Vertically distributed
- Worst case
randomly
2
1
0
12
5x10
3
|VT| [V]
notrap
05ndist_81
rand81
rand81
rand81
uniformly81
1.0ndist_41
rand41
rand41
rand41
uniformly41
1.8ndist_23
rand23
rand23
rand23
uniformly23
1E-5
Uniformly distributed
0
20
40
60
Number of Fixed Charges
80
Simulation results, finding rules of the worst case
Dependence on the average distance between fixed charges
40Vertical
+40 random
0Vertical
+80 random
Abs(Threshold voltage VT) (V)
2.5
20Vertical
+60 random
2.0
1.5
1.0
0.5
0
1
2
3
4
5
Distance between fixed charges (nm)
Abs(Threshold voltage VT) (V)
(vd-1.0 mesh 2A)
Dependence on the one slit with maximum distance
5
4
3
2
1
2
4
6
Distance between fixed charges (nm)
(vd-0.05 mesh 2A)
Probability calculation
Calculation of the WC occurrence probability(permutation)
Probability of a trap in a Cell
= trap density x area of a Cell
Source
Drain
path_1
(xa)
path_4
(xd)
A cell
path_2
(xb)
path_3
(xc)
sample)
x_position
0
1
2
Percolation(potential chain)
Start line
Kind of
percolation
6
8
6

W  2 d or L  x +W  2 d  L  x  (둘중 작은값 ) 
 
 c  a !  exception
2
W /2(  20) 


 W  2 d c or x  c (둘중 작은값) (a  b  c  d )!
 
c !a !
  

,
(
b

40

d

c

a
)

 


a !b !c !d !
 c  a !
 d 0 
c 0
a 0

 

 


c !a !

 


exception =

 x  2i  1!   a  c   x  2i  1 !
 i  1! x  i !  c   i  1 ! a   x  i  ! (i 1)
  x  2i  1 !
 a  c   x  2i  1 !
2! 
 
 e1
 
1!1!   c   i  1 ! a   x  i  !
  i  1 ! x  i  !
( i  2)
  x  2i  1 !
 a  c   x  2i  1 !
4!
2! 
 
 e1
 e2 
 
2!2!
1!1!   c   i  1 ! a   x  i  !
  i  1 ! x  i  !
( i 3)
...(for i=1~(a-x) )
Trap
density
Probability
of the WC
Occurrence
1e11/cm2
1.78E-58
1e12/cm2
1.10E-36
1e13/cm2
3.02E-11
- Probability of the trap existence in a cell :
1e-3 (=1e11/cm2*1e-14cm2)
- Considered distance between traps :
1nm~2nm
 When the probability of a cell becomes
1/1000, probability of the occurrence of
the worst case approaches to
3/100 billion transistors
Physical Validity of the Critical Length for WC
Verifying Physical Validity of Critical Length Method (on going)
-
Calculate potential fluctuation and its effective area due to a single charge through Image charge method
Ref[1]
1
NMOS x0z0 Sentaurus
NMOS x0y0 Sentaurus
Oxide
0.20
x0y0 Matlab
Substrate
Gate
Electrostatic potential (V)
Depletion
layer
Electrostatic potential (V)
0.1
0.01
1E-3
1E-4
x0z0 Matlab
0.15
0.10
0.05
1E-5
0.00
1E-6
-30
-25
-20
-15
-10
-5
0
5
10
depth X (nm)
-30
-20
-10
0
10
20
Length y (nm)
 Electric field of a point charge through three or more dielectrics ,
 Si-SiO2 interface in not a equipotential surface, edge of the depletion region is
equipotential ( symmetry to depletion edge)
- Definitions of effective potential area
- The potential used to describe the scattering center(=screened Coulomb potential) suggested by
BROOKS, HERRING, and DINGLE Ref[2,3]
- How to cut off effective region from a infinite coulomb potential?
-> Partial wave method (low energy scattering)
-> Born approximation method (high energy scattering)
=> How to apply in defining critical length of the worst case?!
[1]T Takashima an, R Ishibashi, IEEE Trans. Electr. Insul, Vol EI-13, No 1, February 1978
[2] Brooks H. , Vol. 7. Academic Press, Inc., New York (1956).
[3] CONWELL E. M and WEISSKOPF V. F. “Theory of impurity Scattering in Semiconductors” Phys. Rev. 77, 388 (1950).
30
향후 계획
5차년도 하반기 (’15.1~’15.6) 주요 연구 계획
- BEOL oxide TDDB

Development of analytic model
- ‘tail’ part modeling of ‘over 1B’ devices
 Defining critical length and verifying Physical validity
 Comparing VT distribution tail of the conventional analytic model with modeling results
 Considering the quantum effect(DG)
12/12