Transcript OR gate produces `1`

Ch 3. Digital Circuits
3.1 Logic Signals and Gates
N bits can represent 𝟐𝑵 states
(When N=1, 2 states)
Input
Output
Black-box
– Black-box representation and Truth table shows a logic circuit
with input/output and ignores electrical behavior of the circuit
– AND gate produces ‘1’ : Only if all of its inputs are ‘1’
– OR gate produces ‘1’ : One or more of its inputs are ‘1’
– NOT gate produces an output that is opposite of its input value
– NAND Gate : Opposite of an AND gate’s output
– NOR Gate : Opposite of an OR gate’s output
Black-box representation
Truth table
Input
Lag
Lag
Lag
Output
𝑿𝒀 + 𝑿′ 𝒀′ 𝒁′
– Timing diagram show how the circuit might respond
to a time-varying pattern of input signals
3.3 CMOS Logic
Not expected to occur except
during signal transition
NMOS
Turn on when 𝑽𝒊𝒏 = 𝟓𝑽
PMOS
Turn on when 𝑽𝒊𝒏 = 𝟎𝑽
High resistance : “Off” Transistor
Low resistance : “On” Transistor
PMOS, Turn on when
𝑽𝒊𝒏 = 𝟎𝑽
NMOS, Turn on when
𝑽𝒊𝒏 = 𝟓𝑽
PMOS
PMOS
NMOS
NMOS
CMOS inverter
둘 중 하나만 On되어도 Z=‘1’
둘 다 On 되어야 Z=‘0’
PMOS
PMOS
PMOS
NMOS
NMOS
NMOS
둘 다 On 되어야 Z=‘1’
둘 중 하나만 On되어도 Z=‘0’
D
𝑽𝒅𝒅
A
PMOS는 F를 이용
PMOS는 F를 이용
B
𝐅=
F=
C
D
FNMOS는
F
A
C
B
D
F’를 이용
NMOS는 F’를 이용
𝑭=
F’ =
AND -> Series
OR -> Parallel
PMOS는 F를 이용
NMOS는 F’를 이용
AND -> Series
OR -> Parallel
𝑨′
Inverter + Inverter
𝑨
𝑨∙𝑩
𝑨∙𝑩
NAND + Inverter
More Transistors are needed than NAND
(𝑨 + 𝑩) ∙ (𝑪 + 𝑫)
𝑨∙𝑩+𝑪∙𝑫
6 Transistor
4 Transistor
6 Transistor
≡
4x3+2 =14 Transistor
16 Transistor
𝑨∙𝑩+𝑪∙𝑫
(𝑨 + 𝑩) ∙ (𝑪 + 𝑫)
6 Transistor
4 Transistor
6 Transistor
≡
4x3+2 =14 Transistor
16 Transistor
3.4 Electrical Behavior of CMOS Circuits
3.5 CMOS Static Electrical Behavior
Noise can be added in signals
So, There are noise margins
𝑽𝑰𝑯𝒎𝒊𝒏 : Min input voltage guaranteed to be recognized as high
High state에서는 Minimum value 고려
𝑽𝑰𝑳𝒎𝒂𝒙 : Max input voltage guaranteed to be recognized as low
Low state에서는 Maximum value 고려
𝑽𝑶𝑳𝒎𝒂𝒙 : Max output voltage produced in low state
𝑽𝑶𝑯𝒎𝒊𝒏 : Min output voltage produced in high state
Not CMOS resistive load
𝑽𝑻𝒉𝒆𝒗 =
𝟐𝒌𝞨
× 𝟓𝑽 = 𝟑. 𝟑𝑽
𝟐𝒌𝞨 + 𝟏𝒌𝞨
𝑽𝑻𝒉𝒆𝒗 =
When 𝑽𝒊𝒏 = 𝟓. 𝟎 𝑽
𝟏𝟎𝟎𝞨
× 𝟑. 𝟑𝟑𝑽 = 𝟎. 𝟒𝟑𝑽
𝟏𝟎𝟎𝞨 + 𝟔𝟔𝟕𝞨
When 𝑽𝒊𝒏 = 𝟎. 𝟎 𝑽
𝑽𝑻𝒉𝒆𝒗 = 𝟓𝑽 − 𝟑. 𝟑𝟑𝑽
𝟐𝟎𝟎𝞨
+ 𝟑. 𝟑𝟑𝑽 = 𝟒. 𝟔𝟏𝑽
𝟐𝟎𝟎𝞨 + 𝟔𝟔𝟕𝞨
𝑹𝒏 𝒐𝒏 ≅
𝑽𝒊𝒏 = 𝟓. 𝟎 𝑽
𝑽𝑶𝑳𝒎𝒂𝒙𝑻
𝑰𝑶𝑳𝒎𝒂𝒙𝑻
𝑹𝒑 𝒐𝒏 ≅
(TTL load)
𝑽𝒊𝒏 = 𝟎. 𝟎 𝑽
𝑽𝑫𝑫 − 𝑽𝑶𝑯𝒎𝒊𝒏𝑻
(TTL load)
𝑰𝑶𝑯𝒎𝒂𝒙𝑻
Sink current
𝑰𝒐𝒖𝒕 =
𝟑. 𝟑𝟑𝑽
= 𝟓. 𝟎𝒎𝑨
𝟎. 𝟔𝟔𝟕𝒌𝞨
Source current
𝑰_𝒐𝒖𝒕 =
𝟓. 𝟎𝑽 − 𝟑. 𝟑𝟑𝑽
= 𝟐. 𝟓𝒎𝑨
𝟎. 𝟔𝟔𝟕𝒌𝞨
Pull-up
𝒁=𝑿∙𝑿=𝑿
𝑿 = 𝟎, 𝒁 = 𝑿 ∙ 𝟏 = 𝟏
𝑿 = 𝟏, 𝒁 = 𝑿 ∙ 𝟏 = 𝑿 = 𝟎
Pull-down
𝑿 = 𝟎, 𝒁 = 𝑿 + 𝟎 = 𝑿 = 𝟏
𝑿 = 𝟏, 𝒁 = 𝑿 + 𝟎 = 𝑿 = 𝟎
No Transition Time in ideal case
𝒕𝒓
(20% ~ 80%)
𝒕𝒇
(80% ~ 20%)
3.6 CMOS Dynamic Electrical Behavior
Both the speed and the power consumption of a CMOS device depend to a large extent on “AC” device
𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 ∙
High State
Low State
−𝒕
𝑹
𝒆 𝒏 𝑪𝑳
𝒕𝒇 = −𝑹𝒏 𝑪𝑳 ∙ 𝒍𝒏
𝑽𝑶𝑼𝑻
𝑽𝑫𝑫
−𝒕
𝑹 𝒑 𝑪𝑳
𝑽𝑶𝑼𝑻 = 𝑽𝑫𝑫 ∙ (𝟏 − 𝒆
Low State
High State
)
𝑽𝑫𝑫 − 𝑽𝑶𝑼𝑻
𝒕𝒓 = −𝑹𝑪 ∙ 𝒍𝒏
𝑽𝑫𝑫
Ideal case (No rise and fall times)
50%
50%
Propagation delay
𝑷𝑻 = 𝑪𝑷𝑫 ∙ 𝑽𝟐𝑪𝑪 ∙ 𝒇 (internal power dissipation due to output transition)
𝑷𝑳 = 𝑪𝑳 ∙ (𝑽𝟐𝑪𝑪 /𝟐) ∙ 𝟐𝒇 (Power due to load capacitor)
𝑷𝑫 = 𝑷𝑻 + 𝑷𝑳 = 𝑪𝑷𝑫 + 𝑪𝑳 ∙ 𝑽𝟐𝑪𝑪 ∙ 𝒇 = 𝑪𝑽𝟐 𝒇
𝒊𝒇 𝑽𝑰𝑵𝟏 , 𝑽𝑰𝑵𝟐 , ⋯ , 𝑽𝑰𝑵𝟖 = 𝑳, 𝒕𝒉𝒆𝒏 𝒂𝒍𝒍 𝟖 𝑽𝒐𝒖𝒕 = 𝑯
𝒊𝒇 𝑽𝑰𝑵𝟏 , 𝑽𝑰𝑵𝟐 , ⋯ , 𝑽𝑰𝑵𝟖 = 𝑯, 𝒕𝒉𝒆𝒏 𝒂𝒍𝒍 𝟖 𝑽𝒐𝒖𝒕 = 𝑳
𝑾𝒉𝒆𝒏 𝑬𝑵 = 𝟏, 𝑨 → 𝑩
𝑾𝒉𝒆𝒏 𝑬𝑵 = 𝟎, 𝑨 → 𝑩
3.7 Other CMOS input and Output Structures
𝟔 𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓
𝑺′
𝟏𝟐 𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓
X
S
Y
S＇
𝑺𝒕𝒂𝒕𝒆 𝒂𝒕 𝟐. 𝟒 𝑽𝒐𝒍𝒕𝒂𝒈𝒆
𝟓. 𝟎𝑽 → 𝟐. 𝟒𝑽 ∶ 𝑳𝒐𝒘
𝟎. 𝟎𝑽 → 𝟐. 𝟒𝑽 ∶ 𝑯𝒊𝒈𝒉
𝑺𝒄𝒉𝒎𝒊𝒕𝒕 − 𝒕𝒓𝒊𝒈𝒈𝒆𝒓 𝒊𝒏𝒗𝒆𝒓𝒕𝒆𝒓
𝒊𝒇 𝑬𝑵 = 𝟎
𝑪 = 𝟏, 𝑩 = 𝟏, 𝑫 = 𝟎
𝑸𝟐 = 𝑸𝟏 = 𝑶𝑭𝑭, 𝑶𝒖𝒕𝒑𝒖𝒕 ← 𝑯𝒊 − 𝒁
𝒊𝒇 𝑬𝑵 = 𝟏
𝑶𝒖𝒕𝒑𝒖𝒕 ← 𝑨
𝑬𝑵 = 𝑳, 𝑶𝒖𝒕𝒑𝒖𝒕 ← 𝑯𝒊 − 𝒁
𝑬𝑵 = 𝑯, 𝑶𝒖𝒕𝒑𝒖𝒕 ← 𝑨
Open-drain output requires an external pull-up resistor
Increase because R=1.5K𝞨
Pull-up Resistor
𝑹=
𝑽𝑪𝑪 − 𝑽𝑶𝑳 − 𝑽𝑳𝑬𝑫 𝟓. 𝟎 − 𝟎. 𝟑𝟕 − 𝟏. 𝟔
=
≈ 𝟑𝟎𝟑𝞨
𝑰𝑳𝑬𝑫
𝟏𝟎𝒎𝑨
𝑾𝒉𝒆𝒏 𝑨 = 𝑩 = 𝟏, 𝒁 = 𝟎, 𝑳𝑬𝑫 𝑶𝑵
𝒊𝒇 𝑬𝒏𝒂𝒃𝒍𝒆𝟑 = 𝑯, 𝑫𝑨𝑻𝑨𝑶𝑼𝑻 ← 𝑫𝑨𝑻𝑨𝟑
𝑶𝒕𝒉𝒆𝒓𝒔 = 𝑳
X
Y
W
𝒊𝒇 𝑿 = 𝒀 = 𝑾 = 𝑯
𝒁 = 𝑯 (AND Function)
𝒊𝒇 𝑨 = 𝑩 = 𝟏 𝒐𝒓 𝑪 = 𝑫 = 𝟏 𝒐𝒓 𝑬 = 𝑭 = 𝟏
𝒁=𝑳
𝒐𝒕𝒉𝒆𝒓𝒘𝒊𝒔𝒆
𝒁=𝑯
Burn !
𝑰𝑶𝑳𝒎𝒂𝒙 = 𝟒𝒎𝑨 (𝑨𝒔𝒔𝒖𝒎𝒑𝒕𝒊𝒐𝒏)
𝑰𝑹𝒎𝒂𝒙 = 𝟒 − 𝟐 ∙ 𝟎. 𝟒 = 𝟑. 𝟐𝒎𝑨
Low output must sink 0.4mA
𝑰𝑰𝑳𝒎𝒂𝒙 = −𝟎. 𝟒 𝒎𝑨
𝑽𝑶𝑳 = 𝟎. 𝟎𝑽 (𝑨𝒔𝒔𝒖𝒎𝒑𝒕𝒊𝒐𝒏)
R 𝒎𝒊𝒏 =
𝟓. 𝟎 − 𝟎. 𝟎
= 𝟏𝟓𝟔𝟐. 𝟓𝞨
𝑰𝑹𝒎𝒂𝒙
𝑰𝑰𝑯𝒎𝒂𝒙 = 𝟐𝟎𝒖𝑨
In high state, typical open-drain outputs have a maximum leakage current 5uA and
typical LS-TTL inputs require 20uA of a source current
𝑰𝑹𝒍𝒆𝒂𝒌 = 𝟒 ∙ 𝟓𝒖𝑨 + (𝟐 ∙ 𝟐𝟎𝒖𝑨) = 𝟔𝟎𝒖𝑨
𝑹𝒎𝒂𝒙 =
𝟓.𝟎−𝟐.𝟒
𝑰𝑹𝒍𝒆𝒂𝒌
= 𝟒𝟑. 𝟑𝒌𝞨
3.8 CMOS Logic Families
High-speed CMOS
High-speed CMOS, TTL compatible
3.9 Low-Voltage CMOS Logic and Interfacing
𝑷𝑫 = 𝑷𝑻 + 𝑷𝑳 = 𝑪𝑷𝑫 + 𝑪𝑳 ∙ 𝑽𝟐𝑪𝑪 ∙ 𝒇 = 𝑪𝑽𝟐 𝒇
Clamp overshoot
0.6V
Clamp undershoot
-0.6V
To Clamp overshoot
Clamp diode
𝑾𝒉𝒆𝒏 𝑽𝒐𝒖𝒕 > 𝑽𝒄𝒄 , 𝑸𝟑 = 𝑶𝑵
𝑽𝟐 ≅ 𝑽𝒐𝒖𝒕 > 𝑽𝒄𝒄
𝑸𝟐 = 𝑶𝑭𝑭, 𝑸𝟏 = 𝑶𝑭𝑭, 𝑻𝒉𝒓𝒆𝒆 − 𝒔𝒕𝒂𝒕𝒆
S
S
OFF
G
S
D
D
D
OFF
G
S
𝒊𝒇 𝑽𝑪𝑪 = 𝟑. 𝟑𝑽, 𝑽𝒐𝒖𝒕 = 𝒀 = 𝟓𝑽
𝐭𝐡𝐞𝐧 𝐐𝟐 𝐛𝐞𝐠𝐢𝐧𝐬 𝐭𝐨 𝐜𝐨𝐧𝐝𝐮𝐜𝐭
(𝐃𝐫𝐚𝐢𝐧 𝐕𝐨𝐥𝐭𝐚𝐠𝐞 > 𝐆𝐚𝐭𝐞 𝐕𝐨𝐥𝐭𝐚𝐠𝐞)
G
D
3.10 Bipolar Logic
AND
pnp
𝑵𝒐𝒕 𝒅𝒆𝒆𝒑𝒍𝒚 𝒔𝒂𝒕𝒖𝒓𝒂𝒕𝒆𝒅
𝟎. 𝟐𝟓𝑽
Path for discharging both
𝑸𝟒′ 𝒔 𝒃𝒂𝒔𝒆 𝒂𝒏𝒅 𝒍𝒐𝒂𝒅 𝒄𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒄𝒆 𝒇𝒓𝒐𝒎 𝒁 = 𝑯 𝒕𝒐 𝑳
Diode AND Gate
Phase Splitter
Output stage
= Totem pole
𝑰𝒏𝒑𝒖𝒕 𝒑𝒓𝒐𝒕𝒆𝒄𝒕𝒊𝒐𝒏
𝑿, 𝒀 ≻ −𝟎. 𝟐𝟓V
𝒊) 𝑬𝒊𝒕𝒉𝒆𝒓 𝒊𝒏𝒑𝒖𝒕 = 𝑳 ≤ 𝟎. 𝟖𝑽
𝑽𝑨 = 𝑽𝑫𝟏𝑿 + 𝑽𝑿 = 𝟎. 𝟐𝟓 + 𝟎. 𝟖 = 𝟏. 𝟎𝟓𝑽 , 𝑸𝟐 𝑶𝑭𝑭
𝒊𝒊) 𝑩𝒐𝒕𝒉 𝒊𝒏𝒑𝒖𝒕 = 𝑯 𝑸𝟐 = 𝑸𝟓 = 𝑶𝑵, 𝑽𝑨 = 𝟏. 𝟐𝑽
𝑪𝒖𝒓𝒓𝒆𝒏𝒕 𝒇𝒍𝒐𝒘𝒔 𝑽𝑪𝑪 → 𝑹𝟐 → 𝑸𝟐 → 𝑸𝟓
𝒊𝒇 𝑽𝑨 ≥ 𝟏. 𝟐, 𝑸𝟐 ∶ 𝑶𝑵
Otherwise ,𝑸𝟐 ∶ 𝑶𝑭𝑭
𝑴𝒖𝒍𝒕𝒊𝒑𝒍𝒆 − 𝒆𝒎𝒊𝒕𝒕𝒆𝒓 𝒕𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓
𝒊𝒏𝒔𝒕𝒆𝒂𝒅 𝒐𝒇 𝒅𝒊𝒐𝒅𝒆𝒔 𝒃𝒚 𝑻𝑰 𝒕𝒐 𝒑𝒆𝒓𝒇𝒐𝒓𝒎 𝑨𝑵𝑫 𝒐𝒑𝒆𝒓𝒂𝒕𝒊𝒐𝒏
𝑳𝒐𝒘
𝑺𝒊𝒏𝒌𝒊𝒏𝒈
𝑪𝒖𝒓𝒓𝒆𝒏𝒕
𝑯𝒊𝒈𝒉
𝑺𝒐𝒖𝒓𝒄𝒊𝒏𝒈
𝑪𝒖𝒓𝒓𝒆𝒏𝒕
𝟎. 𝟕𝑽
1. 𝟐𝑽
𝟎. 𝟑𝑽
𝑪𝑴𝑶𝑺
𝑻𝑻𝑳
𝑻𝑻𝑳
𝑻𝑻𝑳
𝑪𝑴𝑶𝑺