Transcript Home SOC
SOC Development Trends in
Home Applications
Seh-Woong Jeong
April 25 2002
Media SOC Team
System LSI Business
Samsung Electronics Co., Ltd.
Outline of Talk
SOC Development in Samsung System LSI
Issues and Trends in Home Networking
DVD Players/Recorders
Case Study : S5H5002
Q&A
What is SOC ?
Embedded Memory
For Data/Program
RF/Analog
Front End
MODEM/
Channel
MCU
Core
DSP
Core
Hardwired
Logic
Peripheral Interface
Logic
Whole system
in a single package
Driving Forces for SOC’s
Set makers face tough competition to
reduce material cost
New applications need
Low power
Explosive growth of mobile applications
Cellular phones, PDA, ...
Small size
Mobile applications normally mean portability
Reduce number of parts for feature size reduction
High performance
Should cope with system-level complexity
Multi-media applications
SOC Trend
PC
‘00
‘01 ~ ‘02
‘03 ~ ‘05
> 0.25/0.18um
0.13um
< 0.10um
CPU(Cache SRAM)
CPU
PC 1Chip
I/O
SOUND
Graphics(DRAM)
1Chip
RF Rx
BBA Rx
BBA/RF Rx
RF Tx
BBA Tx
BBA/RF Tx
HHP
(CDMA)
Memory
Memory
Memory
PLL
Modem
Modem SRAM
CDMA2000 1x
7Chip
Audio Decoder
TS
Video Decoder
OSGM
Format Converter
5Chip
including
( MP3+AAC+MS+MPEG4 )
BBA/RF Rx
PLL
BBA/RF Tx
DAC+GPS+Bluetooth 4Chip
Modem
PLL
IEEE1394, PCI
Video On a Chip
DTV 1Chip
D-TV
Channel Decoder
Channel EQ.
2Chip
Channel On a Chip
2Chip
1 Chip
Key Ingredients of SOC Technology
Design Methodology
Technology
•Platform-based chip design
•Static timing verification
•HW/SW co-design
•IP Reuse
•DSM logic process
•Embedded memory process
SOC
IP Cores
•MCU, DSP
•DRAM, SRAM, Flash
•High speed I/O
•Analog/RF cores
•Hard / Soft macros
SOC Cooperation
Implementation
•Product / Test engineering
•Packaging technology
Firmware/Software
•Algorithm
•Real time OS
•Device drivers
•System software
•Application software
SOC Requires Tighter Relationship
Strategic Relationship between Set Makers & Silicon Vendors Getting
More Important Than Ever
Early System Requirement Access : Key to Time-to-Market
Working Sample to Design-In : at least 6 months or more
Full Dedication from Both Sides
More System Application Engineers in SOC Vendors
10~20 % more than 50% of R&D Work Force
Strategic Relationship between Silicon Vendors & IP Vendors
Competitive/Proven IP Portfolio : Bare Minimum for SOC Business
You can’t develop everything for yourself !!
Strategic Relationship between Silicon Vendors & Software
Algorithm Firmware
RTOS/Device Driver/BSP/Application Software Support
Hardware Only Makes No Sense to Set-Makers !!
Cooperation Model
Assembly
/ Test
IP Cores
Design
Service
Process
&
Fab
Product
Eng.
System Idea
System
Integration
Silicon
Vendors
Algorithm/
Firmware/
Software
SOC’s
Customers
Samsung SOC Future Goal
Leading The Digital Era
Home
Gateway
Home
Server
N/B
PC
Mobile
Network
Home
Network
DVDP
Digital
TV
PC
MP3
Player
Wireless
PDA
IP
Terminal
Office
Network
Printer
Display
Mobile
Phone
차세대
SOC Solution
SOC 공통 IP
(CPU, DSP, 통신/Media IP)
SOC Infra
(설계방법론, IP Reuse, 인력양성)
SOC 개발/연구
Process
Tech.
Analog
Module
IP &
Library
Package
Product
Engineering
Semiconductor Infra
Design
Service
Home Networking
Why Home Networking ?
From End-User’s Standpoint
9%
Remote Monitoring/Security
13%
Distributed Video
15%
Multiplayer Gaming
17%
Home Control
20%
Connect Laptop from Work
22%
Share Files
23%
Share Printers
26%
Share Internet
0%
5%
10%
15%
20%
25%
30%
Digital Home Example – Cisco View
Home Networking
Home Server + Home Gateway with
•
•
•
Convenient Access to Internet
Easy Connectivity between Home Appliances
Media Streaming Capability with Mass Storage
Each major company has a different view
and its own strategies
•
•
PC-Centric View
CE-Centric View
PC-Centric View – Samsung HMC
Home Media
Center
IEEE1394
Ethernet
PLC
Wireless PAN
CE-Centric View
Home Server + Home Gateway will be
•
•
•
•
Set-Top Box or D-TV
DVD-Box (DVD Player/Recorder or iDVD)
Game Console : PS3 from Sony
“If Sony's aspirations succeed, then the Playstation 3 will not be a pure video game
console, but rather measure the amount of milk left in the fridge, record TV
programs to hard-disk, automatically download new software, perform Tera-flop
operations and a variety of other things. In short, if one can automate, computerize,
network or electrify a process, then the PS3 should be able to take on the task.”
Chances are : some form of a convergence box.
For example,
•
DVD + Set-Top Box with broad-band access capability and
mass storage
Key Technologies
Connectivity Technologies
In-House Connectivity : 802.11e (QoS), IEEE1394, …
• Out-Door Connectivity : xDSL, Cable Modem, ….
• Broadcast Connectivity : VSB, OFDM, QPSK, …
•
Media Processing Technologies
•
•
MPEG2/4 (or H.264)
Pre-/Post-Processing
High Performance CPU/DSP
Middlewares
DVD Players/Recorders
DVD (Digital Versatile/Video Disc/Disk)
An Interesting Article from WP ’02.10.07
“DVD, 할리우드의 최대 수익원으로 부상”
'02년 할리우드 영화의 DVD 판매 및 대여수입은 26억달러로 극장수입 17억달러, 비디오 판매 및 대여
수입 16억달러를 각각 추월하면서 최대 수익원으로 부상
DVD수입 급증은 무엇보다 DVDP 보급 증가에 기인
VCR은 9천만 미국 가구가 보유해 포화 단계인 반면 DVD는 1년 전 천7백만에서 현재 3천백만
가구로 급증
DVD의 경우 VCR과 달리 소비자들이 타이틀 대여보다 구매를 많이 하는 특성이 있어서 판매 확대가 용
이
DVD 보유가구는 올해 평균 260달러 정도의 16개 DVD 타이틀을 구매하는 반면, VCR 보유가구
는 평균 5개의 테이프를 구매
DVD는 대여료 대비 판매가가 3-5배에 그치고, 반영구적인 화질, 제작과정과 게임 등 다양한 컨
텐츠가 있기 때문
디즈니 영화 "몬스터"는 전체 극장수입이 2.6억 달러였지만, DVD를 20달러에 출시한 첫 주에
1.4억달러 가치의 7M copies 판매
DVD는 대량생산이 용이해 제조원가가 적기 때문에 판매 수익도 큼
29.98달러에 팔린 "해리포터" DVD에서 영화사 몫은 9.98달러
11월 1일 출시될 소니의 "스파이더 맨" DVD는 이미 WalMart에만 19M copies 납품 등 새로운
판매기록을 세울 전망
DVD Player System
P/U
Deck Mechanism
RF
(EQ, Digital
Detector)
EFM+ Demod,
ECC Decoder
Video Decoder
(MPEG)
System
Control
Motor
Driver
Servo
(Focus, Tracking,
Sled control)
Front-End
System
Control
Video
CPS
Audio Decoder
(MPEG, AC3, DTS, MLP)
Back-End
Audio
DVD Disc Structures
Single sided Disc
Single side / Single Layer
Single side / Dual Layer
4.7GB
8.5GB
Double side / Single Layer
9.4GB
Double sided Disc
Double Side / Dual Layer
17GB
Optical Disc Evolution
Movement to Higher-Density & Higher-Speed
High-Density
High-Speed
Applications
Technologies
CD
DVD
BD
UD
(Ultra Density)
650 MB
4.7 GB (7 CD)
25/50 GB (6 DVD)
150 GB (6 BD)
1.2 Mbps (1x) ~
57.6 Mbps (48x)
Digital Audio
Infra Red laser
CIRS(Cross
Interleave ReedSolomon) code
EFM
11 Mbps (1x) ~
177 Mbps (16x)
36 Mbps (1x) ~
360 Mbps (10x)
100 Mbps (1x) ~
600 Mbps (6x)
Digital Video (SD)
Digital Video (HD)
QXGA Video
Dual Layer Disc
Red laser
RSPC(ReedSolomon
Product Code)
EFM+
MPEG2/DTS/AC3
Blue laser
LDC(Long
Distance Code)
+ BIC(Burst
Indicator Code)
1.7PP(Parity
Preserve /
Prohibit RMTR)
Multi Layer
Holographic
Near Field
Recording
Movement to Small Form Factor
A smaller disc can store more than 2 hours of Motion
Picture in DVD’s quality (50mm BD or 30mm UD)
DVD Recorder Market Trends
Worldwide DVDP & DVD Recorder Supply (IDC '02. Oct)
Unit: 1M
100
DVD Play-Only DVD Recorder
80
32.21
19.14
(Market Fall off after ’05 is expected)
Rapid Price Drop of DVDP: 30% / Year
( $129(’02) $89(’03) $59(’04) )
9
60
Rapid Market Maturity of Play-Only DVDP
3.06
0.71
40
Market-Shift from VCR to DVD Recorder
0.02
40.9
20
52.2
48.5
52.4
48.7
26.9
Rapid Market Growth after ’03 is Expected
0
2001
(Higher A/V Quality, Affordable Price)
2002
2003
2004
2005
2006
’02
’03
’04
’05
Avant Work
50
170
450
900
IDC
71
306
900
1,914
Fujiwara
60
180
400
800
C/In-Stat
110
280
640
1,360
MEI
130
500
1,150
1,500
Unit: 1M
(Annually more than 200% of Growth)
Popularization of DVDP for Low Price
DVDP Market Saturation
Increase of Needs for Recorders
Recorder Price Down & Market Formation
Market Size & Format Competitions
• In Worldwide DVD Recorder Market, Japan holds 48%, EU holds 32% and US takes 13%
DVD+RW 50%
DVD-RW 20%
EU
DVD-RAM 50%
Japan
DVD+RW 41%
US
DVD-RAM 56%
DVD-RAM 80%
$699
1.0M
1.4M
$499
2.8M
$399
$299
3.8M
◆ Japan
- DVD-RAM + HDD product takes 50% in RAM market
◆ US
- RAM takes 56% in market, +RW increases after ’02.2Q
'02
'03
Japan
'04
EU
US
'05
Others
◆ EU
- Philips (DVD+RW) is a major supplier
Recordable Discs & Features
Super Multi
RAM
IBM
DVD-Multi
- RW
Dell, HP
Panasonic, Toshiba
SAMSUNG, HLDS
SONY
NEC
Sanyo
Pioneer
Ricoh
+ RW
Philips
Yamaha
Mitsumi
± RW
Apple
Sony, Toshiba, Fujitsu
# of Writes
Scan Type
Addressing type
Write type
DVD-RAM
(Panasonic)
100,000
times
Zoned CLV
Single Wobble & PID
Land/Groove
DVD-RW
(Pioneer)
1,000 times
CLV
Single Wobble & Land
Pre-pit
Groove
DVD+RW
(Philips)
1,000 times
CLV
Wobble PM (ADIP)
Groove
DVD Standardization Body
DVD-Forum
Nov. ’97: Changed from ‘Consortium’, Opened publicly
Members: 212 companies over Content Owners, CE
Manufacturers, IT Manufacturers.
Standardized DVD Formats
Logical: DVD-Video, DVD-Audio, DVD-VR, DVD-AR, Streamer
Physical: DVD-ROM, DVD-RAM(3x), DVD-R(4x), DVD-RW(2x)
Discussing proposals for DVD Formats
Logical: Interactive DVD, HD-DVD9, MOST1), iDVD Streamer
Physical: DVD-RAM(5x), DVD-R(8x), DVD-RW(4x), DVD-AOD
BDF (Blue-ray Disc Founders)
Closed consortium to standardize BD-ROM/R/RE format
Member(9 CE companies) + Advisory Group(MPAA, IT, Disc
Manufacturer) + Contributors
1)
Media Oriented Systems Transport
iDVD(Interactive DVD)
DVD-Video Contents + Interactive Contents on Disc
JAVA Script, HTML for Interactive Contents
Value Added Service thru Internet Access
Additional Subtitle Service
Game
E-Commerce
Network Connectivity
(Optional for player)
Contents on
Server
Internet
Connection
Local
Storage
Internet Server
Legarcy DVD
Player Function
Interactiv
Contents
Browsing
iDVD Player
API bridge
DVD-Video contents
iDVD Disc
Interactive
Contents
TV
Samsung A/V Decoder for DVD
S5H5002
S5H5002 Block Diagram
Ethernet
conn.
SDR
SDRAM
NOR Flash
32/16
Memory Controller (32bit 117MHz)
ATAPI
Host/
Parallel
Serial A/V IF
MPEG Stream
Demux
Decoder
MPEG2
Video
Decoder
M1
M2
2D Graphic
Accelerator
ARM
940T
3
2
b
i
t
A
H
B
P
L
U
S
BT 656
in/out
Calm16
MAC2424
(Audio)
IO DMA
M1
M2
IPC
/ Format
Converter
Sub-picture
Decoder
GPIO
3
2
b
i
t
Control
registers
Control
of
IP
registers
Control
of
IP
registers
of IP
A
H
B
P
L
U
S
Mixer
OSD
SPDIF
I2S out
UART
A
P
B
IR
8bit
ADC
I2S in
AHB to
APB
Bridge
I-Frame
Only Encoder
3
2
b
i
t
SPI
I2C
Memory
stick I/F
5
DAC
NTSC/PAL
Encoder
Bus Architecture
SDRAM Bandwidth Problem
Bandwidth-hungry masters contending over an external SDRAM
Single 16-bit SDRAM @ 133MHz used for the cost issue Bandwidth Utilization
Serialized bus transaction in single layer AHB
Utilization = data transfer cycles / total clock cycles
Multi-layer bus is required.
Low SDRAM bandwidth utilization for random access
Access turn around time for each bank : 12 cycles
Maximum utilization : about 60%
Bank interleaving is required.
Single Layer Conventional AHB
Arbitration
SDRAM latency
Data Transfer
Arbitration
SDRAM latency
Multi-Layer AHB
Arbitration
SDRAM latency
Data Transfer
Arbitration
SDRAM latency
Multi-Layer AHB with Bank Interleaving
Arbitration
SDRAM latency
Arbitration
Data Transfer
SDRAM latency
Data Transfer
Data Transfer
Data Transfer
Bus Architecture – AHB+
Backward Compatible with AHB Bus : IP Reuse
Burst Length Extension (1,2,3,5,6,7,8 beats supported)
Hiding Arbitration Overhead
Bus protocol state machine for each master
SDRAM
Memory Controller
Arbiter
Protocol
FSM
Master 1
Protocol
FSM
…
Master 2
Protocol
FSM
Master n
Maximize SDRAM Bandwidth Utilization
Bank interleaving is fully utilized
Address Dependent Priority
Arbiter is tightly coupled with the memory controller
Bus Arbitration Scheme
Priority Scheduling with Ages
Preventing starvation of low priority masters
For each master, latency amount is set by software
If latency is more than the amount, priority is incremented.
Important feature for CPU/DSP
Read/Write transaction requests have higher priority
after read/write transactions, respectively. (in order to
localize the same type of accesses)
Priority Rule
Interface masters have higher priority.
Masters with smaller buffer have higher priority
Usually complex masters need a large buffer.
Masters of higher bandwidth have higher priority
IO DMA > SD Input > VP > FIU > VD > GA
AudioDSP(CalmRISC16+CalmMAC24)
Data Memory
data
16
X
24
Y
24
command
Program
Memory
code
16
CalmMAC24
CalmRISC16
status
CalmMAC24 : Passive Coprocessor to CalmRISC16
Single MDS for CalmRISC16 and Coprocessor CalmMAC24
Programming
Generic Coprocessor Instructions Mapped to a Specific
Coprocessor Instruction Set, in general
CalmADM Design Objectives
Small Area
Low Bus Access Rate
Efficient Stream Data Processing
Caches + Stream Buffers
CalmADM Architecture
Processors:
Memory Subsystems:
Interfaces:
CalmRISC16, CalmMAC24
Three Caches, Two Sequential Stream Buffers
AHB+ Interface, Mail Box
D-Bus
MailBox
32B
CalmRISC16
AHB-Plus
Slave
Host
Processor
PD-Bus
I-Cache
8KB
D-Cache
XC : 6KB
D-Cache
YC : 6KB
CalmMAC24
SBF0 : 16B
SBF1 : 16B
X-Bus Y-Bus
CalmADM
On-Chip
MIU
Arbitor &
AHB-Plus
Master
AHB-Plus
Off-Chip
SDRAM
CalmADM Memory Mapping Scheme
CalmRISC16 Virtual Memory
CalmADM Logical Memory
4M byte
Data Memory
4M byte
Data Memory
Physical Memory
Off-chip Memory
000000h
DBASE
2M byte
Calm area
4:3 data packing
CalmMAC24 Virtual Memory
200000h
220000h
XH
XL
Unused
XE
YH
YL
Unused
YE
XBASE
packed data
4:3 data packing
32K Lword
X Data Memory
240000h
packed data
YBASE
256K byte
SBL0 area
280000h
S0BASE
SBL1 area
32K Lword
Y Data Memory
256K byte
2C0000h
Unused Area
3F0000h
3FFFFFh
64K byte I/O Area
16bit
S1BASE
Data Cache Structure
Y-Cache
X/Y-Caches
X-Cache
Set 2
128
lines
Set1
2-way set associative
Buffered write-back policy
As D-Cache
Calm Area Access
XC/YC are two sets of D-Cache
E bytes are unused
8 24-bit data
E
H
3Byte
L
X/Y Area Access
Address translation for E bytes
Why Stream Buffers?
Off-Chip
Memory
On-Chip
Without Stream Buffers
With Stream Buffers
CPU Core
Input Stream Area
(read-only)
DSP Core
Data
Cache
Temporary Data Area
(read/write)
data address space
of DSP core
Output Stream Area
(write-only)
Off-Chip
Memory
On-Chip
Input Data Area
CPU Core
Stream
Buffer
(read-only)
Extended data
address space
DSP Core
Data
Cache
Stream
Buffer
Temporary Data Area
(read/write)
Output Data Area
(write-only)
data address space
of DSP core
Extended data
address space
Eliminate the overhead of cache
replacement due to stream I/O
Eliminate cache thrashing due to
stream I/O
Separated buffer spaces increase data
space
A Sequential Stream Buffer
16 byte read/write buffer, 16-bit mode / 32-bit mode
Functions for efficient sequential access
Auto-increment of OFFSET address
Empty detection and auto-fill
Full detection and auto-flush
Boundary detection and interrupt generation
On-Chip
Sequential
Buffer 0
Off-Chip
Memory
1
CalmRISC16
+
CalmMAC24
Off-chip
Memory
Data Bus
2
3
Base Address
Buffer Entry
Selection
interrupt
+1
Input/Output
Stream Area
(sequentially
accessed)
Offset
Off-chip
Memory
Address Bus
==
End
Sequential Buffer Module
De-Interlacing(or IPC)
Scan Rate Conversion in DVDP
Source
Progressive
Source
(Film)
Interlaced
Source
(NTSC/PAL)
Display
(Frame Repetition)
Field
Split
Progressive
Display
De-Interlacing
(3:2 or 2:2 Pull down)
Interlaced
Display
De-Interlacing-Cont’d
To display an interlaced video signal on a
progressive display
Method
Bob
Scan line interpolation/duplication using one field
The resulting vertical resolution is limited to the “field”
Weave
merging of two consecutive fields
The simplest method to implement double resolution
Artifacts in regions of movement
3D-IPC(Motion Adaptive IPC)
Field merging for still areas of picture and interpolation for areas of
movement
Issue: cost function to detect a “movement”
MC-IPC(Motion Compensation IPC)
Accurate motion information
Blocky side effect
De-Interlacing-Cont’d
3D-IPC in S5H5002
Temporal
Filtering
Directional
Interpolation
Field I
Field I+1
Field I-1
3 fields
Image
Complexity
SAD
function
Local
motion
Calculate
F(Motion)
Motion inform
Spatio-Temporal
Filtering
Global
motion
WEAVE
3D-IPC
Other Examples
Video Post Processing
for
Image Enhancement
TM
DNIe
Detail Contrast Enhancement
Color Tone Enhancement