Transcript Document 7882461

IP Processing Wrapper
Tutorial
Gigabitkits Workshop August 2001
http://www.arl.wustl.edu/arl/projects/fpx/wrapper/
Gigabit Kits Workshop August 2001
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IP Processing Wrapper Library
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Collection of protocol components in VHDL
Module interface for higher protocol levels
Translation from/to cells to/from higher levels
Components handle protocol checksums and CRCs
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Stacked Wrapper
Application
Wrapper
Wrapper
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The Cell-Processor
•
•
•
•
Checks the HEC and drops erroneous cells
Dispatch cells to application or bypass
Handles control cells
Recomputes HEC for outgoing cells
HEC
Dispatch
Check
HEC
Set
Control
Cells
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AAL5 Frame Processor
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•
•
Frame Processor detects frame boundaries
FP handles CRC
FP segments data into cells
Cell
Frame
AAL5CRC
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Segment
ation
Detection
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AAL5CRC
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IP Processor
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•
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•
ATM Header
Ver HL ToS
IPID
TTL
Packet Length
Fragment
Proto
Checksum
Source IP address
IP Header
•
Verify IP version
Check Header Checksum for application (ev. Drop)
Decrease TTL field (ev. ICMP msg)
Signal start of payload (SOP)
Recompute Header Checksum
Destination IP address
IP Detect
+
Checksum
TTLDec
Checksum
Payload
IPProcessor
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UDP Processor
•
•
•
Check for protocol ID (17)
Signal start of datagram (SOD)
Handle UDP checksum
ATM Header
Ver HL ToS
IPID
TTL
Proto
Packet Len
Fragment
IP Header
Checksum
Source IP address
UDP
Detect
Set
Checksum
Destination IP address
Src Port
Dest Port
Length
Checksum
UDP Header
Payload
UDPProcessor
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Space & Speed
Space/LUTs
Cell Processor
Speed/MHz
781
125
Frame Processor
1251
116
IP Processor
1009
109
550
114
UDP Processor
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Delays
Delay for short packages
Delay for long packages
Input
Input
output
output
Cell
Processor
4
6
4
6
Frame
Processor
21
22
10
31
IP Processor
36
39
24
197
UDP
Processor
39
44
27
202
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Throughput
Throughput for short
packages
Throughput for long
packages
Input
Input
output
output
Cell
Processor
4
6
4
6
Frame
Processor
21
22
10
31
IP Processor
36
39
24
197
UDP
Processor
39
44
27
202
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Downloading the library
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Download at http://www.arl.wustl.edu/arl/fpx/wrapper/
VHDL simulation files
edif files for synthesis
VHDL wrapper files
» Combine several layers for convenience
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Cell Wrapper files
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Cellprocessor.edn
» Synthesized cell processor
» Use during place & route of your design
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Cellprocessor.vhdl
» Structural simulation file
» Use during simulation of design
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Frame Wrapper Files
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Frameprocessor.edn
» Synthesized frame processor
» Use during place & route of your design
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Frameprocessor.vhdl
» Structural simulation file
» Use during simulation of design
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Framewrapper.vhdl
» Combine the frame processor with the cell processor
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IP Wrapper Files

ipprocessor.edn
» Synthesized IP processor
» Use during place & route of your design

ipprocessor.vhdl
» Structural simulation file
» Use during simulation of design

ipwrapper.vhdl
» Combine the ip processor with the frame wrapper
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UDP Wrapper Files

udpprocessor.edn
» Synthesized UDP processor
» Use during place & route of your design
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udpprocessor.vhdl
» Structural simulation file
» Use during simulation of design

udpwrapper.vhdl
» Combine the UDP processor with the IP wrapper
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UDP Application
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General signals
 CLK (clock signal)
 Reset_l (synchronous reset, active low)
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Input signals
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»
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»
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»
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D_MOD_IN (data input)
DataEn_MOD_IN (data enable)
SOF_MOD_IN (start of frame)
SOD_MOD_IN (start of datagram)
EOF_MOD_IN (end of frame)
TCA_MOD_IN (congestion control)
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Output signals
»
»
»
»
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D_OUT_MOD (data output)
DataEn_OUT_MOD (data enable)
SOF_OUT_MOD (start of frame)
SOD_OUT_MOD (start of datagram)
EOF_OUT_MOD (end of frame)
TCA_OUT_MOD (congestion control)
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Clock & Reset
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CLK
» Clock signal for module
» 100 MHz
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Reset_l
» Synchronous reset
» Low for 1 clock cycle to reset state machines
» Set by reconfiguration logic
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Data
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D_MOD_IN + D_OUT_MOD
» Data bus
» 32 bit wide
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DataEn_MOD_IN + DataEn_OUT_MOD
» Hi during valid payload data
» Hi during trailer words (after EOF)
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Boundary signals
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SOF_MOD_IN + SOF_OUT_MOD
» Hi for 1 clock cycle during first ATM header word
» Signals start of a new AAL5 frame
» Note: HEC is not sent after this signal
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SOD_MOD_IN + SOD_OUT_MOD
» Hi for 1 clock cycle during first word of UDP header
» UDP payload starts after two valid payload words (check Data
Enable)
» Not enabled if not a UDP packet
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EOF_MOD_IN + EOF_OUT_MOD
» Hi during 1 clock cycle of last payload word of datagram
» Followed by the two trailer words of the AAL5 frame
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Congestion Control
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TCA_MOD_IN + TCA_OUT_MOD
» TCA signal is hi when data can be accepted, lo if no data should be
sent
» Wrappers back-propagate TCA to the NID
» Data in pipeline will still be forwarded (~cell time)
» IP wrapper has big packet buffer for outgoing data
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Signals
CLK
A A
I
I
I
I
I
U U D D D D D -
-
A A D D D D D D D P
P
P
F
F
-
-
A -
I
I
I
I
I
U U D D D D D -
-
-
F
-
-
-
-
-
SOC
Data
-
D D D D D D D F
Cell Level
Data
SOF
IP Level
Frame Level
DataEn
EOF
SOP/
SOD
A
ATM Header
I
IP Header
D
Payload Data
-
Don't care
U
UDP Header
P
Padding
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F
Frame Trailer
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Integrate Application
UDP Wrapper
Input
Application
Output
UDP Processor
IP Processor
Frame Processor
Cell Processor
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Configuration
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Simulation
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RAD
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Application (with wrappers)
Reconfiguration logic (reset and
repramming)
Control Cell Processor (if
needed for SRAM/SDRAM
access)
SRAM/SDRAM controller (if
needed)
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RAD
Ingress
Ingress
Application
Port
Port
Reconfig
Control
SRAM
Interface
Egress
Control
Port
Cell
Processor
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SRAM
Egress
Port
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Synthesis
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Add VHDL files for application
Set part to “Xilinx Virtex 1000E fg680”
Synthesize
E.g. Synplicity/Synplify
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Place & Route
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Copy wrapper-edif files (*.edn) to target directory
“ngdbuild –p xcv1000e-7-fg680 design –uc design.ucf”
“map –p xcv1000e-7-fg680 –o top.ncd design.ncd design.pcf”
“par –w –ol 2 top.ncd design.ncd design.pcf”
“bitgen design.ncd –b –l –w –f bitgen.ut”
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Downloading bitfile to FPX
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Connect JTAG cable to FPX
Select bitmap file in JTAG programmer
Program chip
Reset switch (NCHARGE on http://fpx.arl.wustl.edu)
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