Transcript The ALMA Data Transmission – Digital Portion System Chris Langley

The ALMA Data Transmission
System – Digital Portion
Chris Langley
ALMA Back End Integrated Product Team
5 - 8 January 2009
National Radio Science Meetings
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The Challenge
Transmit 4 – 12 GHz
Astronomical Data from the Front End (FE) Band
Cartridges to the Correlator using Commercial Off
The Shelf equipment wherever possible.
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The Challenge
Transmit 4 – 12 GHz
Astronomical Data from the Front End (FE) Band
Cartridges to the Correlator using Commercial Off
The Shelf equipment wherever possible.
The Proposal
Convert FE data Digitally and Optically prior to
transmission from each of 66 antennas.
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The Flaw
COTS, or any other, D/A converters capable of
4 – 12 GHz inputs were not available during R&D.
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The Flaw
COTS, or any other, D/A converters capable of
4 – 12 GHz inputs were not available during R&D.
The Solution
Separate, or Down Convert, the 4 – 12 GHz two
polarity band into eight 2 – 4 GHz basebands
prior to data conversion and transmission.
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Astronomical Data Down Conversion &
Transmission
256 bits @
125 MHz
BB 0
BB 0
USB
BB 2
P0
BB 0
DTX 0
DRX 0
BB 1
BB 1
P0 IFDC
LSB
BB 4
BB 6
4-12 GHz
DTX 1
BB 1
BB 3
DRX 1
BB 3
Virtual Parallel Bus
BB 3
10 Gb/s X 12
≤ 15 Km
BB 4
BB 4
2-4 GHz
USB
P1
BB 2
BB 2
DTX 2
DRX 2
BB 5
BB 5
P1 IFDC
LSB
BB 5
BB 7
BB 6
BB 6
DTX 3
BB 7
BB 7
Front
End
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DRX 3
Correlator
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Data Transmission System
256 bits @
125 MHz
BB 0
BB 0
USB
BB 2
P0
BB 0
DTX 0
DRX 0
BB 1
BB 1
P0 IFDC
LSB
BB 4
BB 6
4-12 GHz
DTX 1
BB 1
BB 3
DRX 1
BB 3
Virtual Parallel Bus
BB 3
10 Gb/s X 12
≤ 15 Km
BB 4
BB 4
2-4 GHz
USB
P1
BB 2
BB 2
DTX 2
DRX 2
BB 5
BB 5
P1 IFDC
LSB
BB 5
BB 7
BB 6
BB 6
DTX 3
BB 7
BB 7
Front
End
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DRX 3
Correlator
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Design Considerations (1/2)
• Operate at OC-192 (9.95328Gb/s) optical fiber signaling
speed
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Design Considerations (1/2)
• Operate at OC-192 (9.95328Gb/s) optical fiber signaling
speed
• Use of time division digital multiplexing to transform the
input signaling rate to the channel signaling rate
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Design Considerations (1/2)
• Operate at OC-192 (9.95328Gb/s) optical fiber signaling
speed
• Use of time division digital multiplexing to transform the
input signaling rate to the channel signaling rate
• Insertion of fill bits to convert input rate to signaling rate
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Design Considerations (1/2)
• Operate at OC-192 (9.95328Gb/s) optical fiber signaling
speed
• Use of time division digital multiplexing to transform the
input signaling rate to the channel signaling rate
• Insertion of fill bits to convert input rate to signaling rate
• Use of time division digital de-multiplexing to transform
the channel signaling rate to the output signaling rate
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Design Considerations (1/2)
• Operate at OC-192 (9.95328Gb/s) optical fiber signaling
speed
• Use of time division digital multiplexing to transform the
input signaling rate to the channel signaling rate
• Insertion of fill bits to convert input rate to signaling rate
• Use of time division digital de-multiplexing to transform
the channel signaling rate to the output signaling rate
• Elimination of un-needed fill bits upon reception
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Design Considerations (1/2)
• Operate at OC-192 (9.95328Gb/s) optical fiber signaling
speed
• Use of time division digital multiplexing to transform the
input signaling rate to the channel signaling rate
• Insertion of fill bits to convert input rate to signaling rate
• Use of time division digital de-multiplexing to transform
the channel signaling rate to the output signaling rate
• Elimination of un-needed fill bits upon reception
• Use of three OC-192 channels per 2 GHz baseband to
achieve required capacity
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Design Considerations (2/2)
• Low-voltage differential signaling (LVDS)
– Fast rise/fall times
– Noise resistant
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Design Considerations (2/2)
• Low-voltage differential signaling (LVDS)
– Fast rise/fall times
– Noise resistant
• Multiple FPGA design per channel
– More economical than single FPGA
– Ball Grid Array package  Lots of IO
– 625+ MHz input signal capability
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Design Considerations (2/2)
• Low-voltage differential signaling (LVDS)
– Fast rise/fall times
– Noise resistant
• Multiple FPGA design per channel
– More economical than single FPGA
– Ball Grid Array package
– 625+ MHz input signal capability
• Commercial Optical “Half” Transponders
– Change from original design
– Became economical
– Built in mux /demux, clock recovery
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Design Considerations (2/2)
• Low-voltage differential signaling (LVDS)
– Fast rise/fall times
– Noise resistant
• Multiple FPGA design per channel
– More economical than single FPGA
– Ball Grid Array package
– 625+ MHz input signal capability
• Commercial Optical “Half” Transponders
– Economical
– Built in mux /demux, clock recovery
• Air cooled (flow through) module, RFI shielded (-50
dBm)
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5 - 8 January 2009
124 bits
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checksum
4 bits 4 bits
124 MSB’s of payload
MSB’s of sync pattern
5 bits
4 LSB’s of payload
6 bits
Sequence count
Metaframe index (1 bit)
LSB’s of sync pattern
BIT 159
BIT 144
BIT 20
MSB (last bit)
MSB of payload
LSB (first bit)
LSB of payload
BIT 12
BIT 16
LSB
LSB (first bit)
BIT 6
BIT 7
BIT 0
Data Frame Organization
16 bits
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Data Transmission System
Closer View
3-bits X 16
@ 250 MHz
X4
2 – 4 GHz
P0
1-bit X 10 Gb/s
X 12
3-bits X 32
@ 125 MHz
X4
D (+/-)
3-bit
Digitizer
P0
C
3-bit
Digitizer
P1
DRX 0
Optical
Receivers &
DeFormatter
B
4 GHz
2 – 4 GHz
P1
120 Gb/s
1-bit X 10 Gb/s
X 12
D (+/-)
Formatter &
Optical
Transmitters
C
B
DTX 0
DTX 1
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Fiber
Optic
MUX
EDFA
Fiber
Optic
DeMutiplexer
DRX 1
DTX 2
DRX 2
DTX 3
DRX 3
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Data Transmitter Module
(Digitizer and Formatter, 4 per Antenna)
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15.0 VDC
5.0 VDC
3.3 VDC
-5.2 VDC
5.0 VDC
3.3 VDC
Data Transmitter Module
4 / Antenna
Backplane
DG
From IFP
P0
P0
- 10 dB
3 bit
A/D
To FOM
FR
1:16
Demux
1:16
Demux
FPGA
B
TXP
FPGA
D
TXP
FPGA
C
TXP
B Bits
ITU Wavelength
21, 27, 33, or 39
1:16
Demux
2.13-3.95 GHz
0 +/- 1 dBm
D Bits
ITU Wavelength
25, 31, 37, or 43
1:16
Demux
P1
P1
- 10 dB
3 bit
A/D
1:16
Demux
1:16
Demux
C Bits
ITU Wavelength
23, 29, 35 or 41
Power
Harness
PCB
SPI DG
250 MHz, 15.6 psec
stepped delay, 0 dBm
-5.2 VDC
3.3 VDC
SPI
From DGCK
LRU
4 GHz, 15.6 psec
stepped delay, 0 dBm
48 VDC
125 MHz, 0 dBm
MCPS
48ms, LVDS
From FOM
From PSAC
Optical Keep Alive
AMBSI-2
48 VDC
From ABM
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5.0 VDC
15.0 VDC
PWR
FILTERS
AMB 0x5X, X = 0, 1, 2, 3
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Digitizer Assembly
University of Bordeaux
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Formatter with 3 Optical Transmitting
Transponders
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Data Receiver Module
(De-Formatter with 3 Optical Receiving Transponders)
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Data Receiver Module
4 / Antenna
Steering Clk
-5.2 VDC
156.25 MHz
1.8 VDC
1.5 VDC
3.3 VDC
3.3 VDC
5.0 VDC
Data (D Bits)
RX Transponder with
1:16 DeMux
P0
FPGA
Altera EP1S20F780C5 D Bits
16 bits @ 625 Mb/s
32 bits each @ 125
MHz
P1
Recovered Data Clk
625 MHz
From FOAD
10 Gb/s
SPI
Steering Clk
JTAG Chain
FPGA Comm.
-5.2 VDC
156.25 MHz
1.8 VDC
1.5 VDC
3.3 VDC
3.3 VDC
5.0 VDC
Data (C Bits)
RX Transponder with
1:16 DeMux
P0
FPGA
Altera EP1S20F780C5 C Bits
16 bits @ 625 Mb/s
32 bits each @ 125
MHz
P1
Recovered Data Clk
625 MHz
From FOAD
10 Gb/s
SPI
Steering Clk
FPGA Comm.
To / From Correlator
Station Bin Motherboard
JTAG Chain
-5.2 VDC
156.25 MHz
1.8 VDC
1.5 VDC
Control Bits
3.3 VDC
3.3 VDC
5.0 VDC
Data (B Bits)
RX Transponder with
1:16 DeMux
P0
FPGA
Altera EP1S20F780C5 B Bits
16 bits @ 625 Mb/s
32 bits each @ 125
MHz
P1
Recovered Data Clk
From FOAD
625 MHz
10 Gb/s
125 MHz
I2C Bus
SPI
JTAG Chain
48 ms
5.0 VDC
3.3 VDC
1.8 VDC
1.5 VDC
-5.2 VDC
5.0 VDC
AMBSI-2
3.3 VDC
Configuration EEPROM
Altera EPC16QC100
3.3 VDC
From Station Bin Motherboard
DC Power Regulation
AMB
48 VDC
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DTS Modules for 1 Antenna
Digitizer
Clock
IRAM,
NRAO
Fiber Optic
Multiplexer
Data
Transmitters
Jodrell Bank
Observatory
Fiber Optic
Amplifier /
Demultiplexer
Jodrell Bank
Observatory
U of Bordeaux,
NRAO
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Data
Receivers
NRAO
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DTS Link Tests - ALMA Antenna to Lab
Chile, 8/2008
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DTS Link Tests - ALMA Antenna to Lab
Chile, 8/2008
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Things We’d Do Differently …
• Single FPGA per channel!
– FPGA logic timing is difficult
– Economics will likely catch up
• Closer interaction between hardware and firmware
designers
– Each should be the other’s backup
• Invite external expert’s opinions sooner during the
design process
• Test Stand
– Design and build once assembly form factors are determined
• Communication between remote team members was
good, but could have been better
– Specify an early DTS design review for the international partners
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Acknowledgements
• Robert Freund, Principle Engineer, Arizona Radio Observatory
• Paula Metzner, DTS Product Engineer, Atacama Large Millimeter
Array, National Radio Astronomy Observatory
… and the entire DTS teams from North America, the University of
Bordeaux, IRAM (Grenoble, FR), and Jodrell Bank Observatory
(~Manchester, UK).
References
R. W. Freund, ALMA Memo 420: Digital Transmission System Signaling
Protocol, 2002
R. W. Freund and C. Langley, BE Critical Design Review, 2004.
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Auxiliary Slides
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Data Transmission System Overview
The Partners
Antennas 2- 50
From
IFP,
2-4
GHz,
Two
Polarities
UB Effort
UK Effort
DG
(4)
FR
TXT
(4)
Antenna 1
FO
Mux
12
1
10 GB/s
Fibers
1
US Effort
Cable
120 GB/s
Fibers
LO M/C Fibers
15 Km
~185 Similar Cables
Antennas & Sites
Control Building
FO
Patch
Panel
~186 Cables
50
Cables
12
Fibers
49
Fibers
Fibers
To FOAD
#2 - #50
LO, M/C Fibers
1
Fiber
FOAD
Ant #1
50
Splice
Rack
2 base bands x 96
bits
@ 125 MHz
DFR
RXT
(4)
To FIR/Correlator
Positions for 49
more Antennas
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System Requirements
• Repeatable latency with no loss of samples
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System Requirements
• Repeatable latency with no loss of samples
• Bit error rate < 10-6 (End of Life)
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System Requirements
• Repeatable latency with no loss of samples
• Bit error rate < 10-6 (End of Life)
• Multi-channel synchronization loss < 10-4 s
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System Requirements
•
•
•
•
Repeatable latency with no loss of samples
Bit error rate < 10-6 (End of Life)
Multi-channel synchronization loss < 10-4 s
16 GHz analog bandwidth source
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System Requirements
•
•
•
•
•
Repeatable latency with no loss of samples
Bit error rate < 10-6 (End of Life)
Multi-channel synchronization loss < 10-4 s
16 GHz analog bandwidth source
Nyquist sampled data
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System Requirements
•
•
•
•
•
•
Repeatable latency with no loss of samples
Bit error rate < 10-6 (End of Life)
Multi-channel synchronization loss < 10-4 s
16 GHz analog bandwidth source
Nyquist sampled data
3-bit data word
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System Requirements
•
•
•
•
•
•
•
Repeatable latency with no loss of samples
Bit error rate < 10-6 (End of Life)
Multi-channel synchronization loss < 10-4 s
16 GHz analog bandwidth source
Nyquist sampled data
3-bit data word
Data transmission synchronized with ALMA
timing
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System Overview
Explicit requirements
• 4 GSa/s per 2 GHz bandwidth IF channel
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System Overview
Explicit requirements
• 4 GSa/s per 2 GHz bandwidth IF channel
• 3 bits per sample
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System Overview
Explicit requirements
• 4 GSa/s per 2 GHz bandwidth IF channel
• 3 bits per sample
• 2 Polarizations x 4 IF channels
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System Overview
Explicit requirements
•
•
•
•
4 GSa/s per 2 GHz bandwidth IF channel
3 bits per sample
2 Polarizations x 4 IF channels
96 Gb/s per antenna (120 Gb/s encoded data)
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System Overview
Explicit requirements
•
•
•
•
•
4 GSa/s per 2 GHz bandwidth IF channel
3 bits per sample
2 Polarizations x 4 IF channels
96 Gb/s per antenna (120 Gb/s encoded data)
250 MHz input word rate (96-bit wide parallel word)
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System Overview
Explicit requirements
•
•
•
•
•
•
4 GSa/s per 2 GHz bandwidth IF channel
3 bits per sample
2 Polarizations x 4 IF channels
96 Gb/s per antenna (120 Gb/s encoded data)
250 MHz input word rate (96-bit wide parallel word)
125 MHz output word rate (192-bit wide parallel
word)
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System Overview
Explicit requirements
•
•
•
•
•
•
4 GSa/s per 2 GHz bandwidth IF channel
3 bits per sample
2 Polarizations x 4 IF channels
96 Gb/s per antenna (120 Gb/s encoded data)
250 MHz input word rate (96-bit wide parallel word)
125 MHz output word rate (192-bit wide parallel
word)
• Grouping of a polarization pair: 24 Gb/s per pair
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System Overview
Explicit requirements
•
•
•
•
•
•
4 GSa/s per 2 GHz bandwidth IF channel
3 bits per sample
2 Polarizations x 4 IF channels
96 Gb/s per antenna (120 Gb/s encoded data)
250 MHz input word rate (96-bit wide parallel word)
125 MHz output word rate (192-bit wide parallel
word)
• Grouping of a polarization pair: 24 Gb/s per pair
• Walsh function 180° switching
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System Overview
Explicit requirements
•
•
•
•
•
•
4 GSa/s per 2 GHz bandwidth IF channel
3 bits per sample
2 Polarizations x 4 IF channels
96 Gb/s per antenna (120 Gb/s encoded data)
250 MHz input word rate (96-bit wide parallel word)
125 MHz output word rate (192-bit wide parallel
word)
• Grouping of a polarization pair: 24 Gb/s per pair
• Walsh function 180° switching
• 15 Km (maximum) distance
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System Overview
Implied requirements
• Configurable if not deterministic timing (repeatable
latency)
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System Overview
Implied requirements
• Configurable if not deterministic timing (repeatable
latency)
• Fast frame synchronization
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System Overview
Implied requirements
• Configurable if not deterministic timing (repeatable
latency)
• Fast frame synchronization
• Continuous transmission of data
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System Overview
Implied requirements
• Configurable if not deterministic timing (repeatable
latency)
• Fast frame synchronization
• Continuous transmission of data
• Low error rates throughout operational life
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System Overview
Implied requirements
• Configurable if not deterministic timing (repeatable
latency)
• Fast frame synchronization
• Continuous transmission of data
• Low error rates throughout operational life
• Operation independent of payload content
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System Overview
Implied requirements
• Configurable if not deterministic timing (repeatable
latency)
• Fast frame synchronization
• Continuous transmission of data
• Low error rates throughout operational life
• Operation independent of payload content
• Testing strategies
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System Overview
Implied requirements
• Configurable if not deterministic timing (repeatable
latency)
• Fast frame synchronization
• Continuous transmission of data
• Low error rates throughout operational life
• Operation independent of payload content
• Testing strategies
• Economical implementation
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Auxilary Slides
DTS Single Bit Data Path
(VHDL Top Level)
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Frame Implementation
•
•
•
•
•
•
160 bit frame
128-bit payload
10-bit synchronization word
5-bit meta-frame sequence word
1-bit meta-frame index
16-bit odd parity check word
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Design Decisions
• Use of a data block (frame) to facilitate multiplexing
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Design Decisions
• Use of a data block (frame) to facilitate multiplexing
• Use of a synchronization (framing) word to facilitate
frame detection
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Design Decisions
• Use of a data block (frame) to facilitate multiplexing
• Use of a synchronization (framing) word to facilitate
frame detection
• Use of scrambling techniques to minimize bit sequence
effects, low frequency content, and to maintain signal
balance
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Design Decisions
• Use of a data block (frame) to facilitate multiplexing
• Use of a synchronization (framing) word to facilitate
frame detection
• Use of scrambling techniques to minimize bit sequence
effects, low frequency content, and to maintain signal
balance
• Use of a meta-frame to synchronize the reception of
multiple channels
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Design Decisions
• Use of a data block (frame) to facilitate multiplexing
• Use of a synchronization (framing) word to facilitate
frame detection
• Use of scrambling techniques to minimize bit sequence
effects, low frequency content, and to maintain signal
balance
• Use of a meta-frame to synchronize the reception of
multiple channels
• Use of a meta-frame index to synchronize reception to
ALMA timing under varying propagation delays
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Design Decisions
• Use of a data block (frame) to facilitate multiplexing
• Use of a synchronization (framing) word to facilitate
frame detection
• Use of scrambling techniques to minimize bit sequence
effects, low frequency content, and to maintain signal
balance
• Use of a meta-frame to synchronize the reception of
multiple channels
• Use of a meta-frame index to synchronize reception to
ALMA timing under varying propagation delays
• Use of a checksum word to facilitate continuous
monitoring of received data integrity
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Auxilary Slides
DTX Formatter FPGAs and Transponders
DIGITIZER
u100
TTX 1
BB0A
BB1A
BB0
16
4GHz
BB1
16
TTX FRAME DATA D
DATA
625 MHz
CLK
ADC
SPI
FIBER
10 GBs
D
FRAMECLK
250MHz
phase shifted
SPI
AMBSI
u200
BB0
16
BB1
16
TE GEN
625 MHz
AMBSI SPI
DIGITIZER SPI
FRAME
SYNC
CLOCK
DIVIDER
16
TTX 2
TTX FRAME DATA C
FRAMECLK
DATA
625 MHz
CLK
TTX SPI
SPI
FIBER
10 GBs
C
SPI
TESYS
TE GEN
AMBSI SPI
FRAME
SYNC
SYSCLK
625 MHz
TTX 3
u300
BB0
16
BB1
16
FRAMECLK
TTX FRAME DATA B
625 MHz
DATA
FIBER
10 GBs
CLK
B
SPI
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625 MHz
64
Auxilary Slides
DRX De-Formatter FPGAs and Transponders
TRX 1
FIBER
10 GBs
DATA
BOT_A
16
TRX MUX’D DATA D
32
625 MHz
32
CLK
BB0
BB1
D
REF CLK
FIBER
10 GBs
DATA
TE GEN
AMBSI SPI
MID_B
16
FRAME SYNC
TRX 2
FRAME COUNT
I2C
32
TRX MUX’D DATA C
625 MHz
CLK
BB0
32
BB1
C
CORRELATOR
DATA
196 BITS @
125 MHz
REF CLK
TRX 3
FIBER
10 GBs
DATA
TOP_C
16
TE GEN
FRAME SYNC
AMBSI SPI
TE
SPEC DELAY
FRAME COUNT
I2C
TRX MUX’D DATA B
32
625 MHz
32
CLK
BB0
BB1
B
REF CLK
I2C
4 TRX I2C
SPI
EEPROM
SYSCLK
AMBSI
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Auxiliary Slides
Frame Synchronizations
►Frame synchronization (10-bit synchronization
word)
• Multi-channel synchronization (5-bit meta-frame
sequence word)
• Determination of propagation delay (1-bit metaframe index)
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Auxilary Slides
Frame Synchronizations
• Frame synchronization (10-bit synchronization word)
• Multi-channel synchronization (5-bit meta-frame
sequence word)
• Determination of propagation delay (1-bit meta-frame
index)
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Auxiliary Slides
Frame synchronization (10-bit synchronization
word)
• Unique or “unique enough” pattern to minimize
acceptance of erroneous patterns in random data
• Long enough pattern to eliminate the acceptance of
erroneous pattern in static data
• Partitioned pattern to eliminate the acceptance of a
correct pattern in an incorrectly configured system
• Three acceptance stages required to qualify a 10-bit
quantity as the synchronization pattern
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Auxiliary Slides
Stages for Frame Synchronization
• Search:
selection of an initial location within the serial bitstream followed by the shifting of the location until a
candidate synchronization word is located
• Check:
continued observations in subsequent frames until
unsuccessful criterion (failure)
• Monitor:
once confirmed, continuous monitoring of all frames
to ensure proper operation
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Auxiliary Slides
Frame Synchronizations
• Frame synchronization (10-bit synchronization
word)
►Multi-channel synchronization (5-bit meta-frame
sequence word)
• Determination of propagation delay (1-bit metaframe index)
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Auxiliary Slides
Multi-channel synchronization (5-bit meta-frame
sequence word)
• Sequence word large enough to accommodate
worst case relative variation in propagation delay
across the three channels
• Integer number of meta-frames contained within one
48.000ms timing period
• Transmitter simultaneously writes the identical
incrementing sequence number in frames of all
three channels
• Receiver compares and re-times the frames from
the three channels thus synchronizing the metaframes
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National Radio Science Meetings
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Auxiliary Slides
Frame Synchronizations
• Frame synchronization (10-bit synchronization
word)
• Multi-channel synchronization (5-bit meta-frame
sequence word)
►Determination of propagation delay (1-bit metaframe index)
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National Radio Science Meetings
72
Auxiliary Slides
Determination of propagation delay (1-bit metaframe index)
• Transmitter uniquely identifies the first metaframe following a 48.000ms timing event
• Monitor and Control system obtains the count of
frames received following the local 48.000ms
timing event and the detection of the meta-frame
index bit
• Monitor and Control system command the
receiver to adjust its internal frame delay to a
specific relative value
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National Radio Science Meetings
73
Auxilary Slides
Scrambling
• Modification of source data to accommodate specific
characteristics of the communication channel
• Provides adequate timing for the clock and data recovery
electronics
• Provides a signal balance for the AC coupled circuits
which minimizes threshold errors
• Pattern is easily produced by a maximally length shift
register generator
• Sync word is exempt from scrambling
• For 149 -> 0, Result <= output pattern (shifted +1) XOR
input pattern
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National Radio Science Meetings
74
Auxilary Slides
Data Integrity
•
•
•
•
Parity computation is easier than CRC
16-bit parity word over 144 bits
Each parity bit monitors 9 other bits
Permits continuous monitoring of transmission quality
5 - 8 January 2009
National Radio Science Meetings
75
Auxiliary Slides
Self Test Methods
•
•
•
•
•
•
•
10 GHz clock recovery
Frame detection
Multiple channel synchronization
Scrambled pattern exercises
Random Number Generation
Checksum (parity) checks
FFT of pseudo Front End data (gain flatness,
CW beacon)
5 - 8 January 2009
National Radio Science Meetings
76
Formatter Block Diagram
250 Mb/s
(32 bits)
From Digitizer
Assembly
62.5 Mb/s
(128 bits)
625 Mb/s
(16bits)
62.5 Mb/s
(160 bits)
10 Gb/s
(1bit optical)
P0
P1
1:4 Demux
Protocol
Encoder
Sixteen
10:1 Mux’s
Half
Transponder
Protocol
Encoder
Sixteen
10:1 Mux’s
Half
Transponder
To FOM
FPGA 1
P0
P1
1:4 Demux
Laser Keep Alive
From FOM
To / From Digitizer
Assembly
MC
Engine
FPGA 2
To / From MC / PS
Board
P0
P1
-5.2 VDC
From MC / PS
Protocol
Encoder
Sixteen
10:1 Mux’s
Half
Transponder
FPGA 3
5 VDC
15 VDC
3.3 VDC
From DGCK
1:4 Demux
625 MHz
DC-DC
Converters
Monitor Point
A/D’s & Mux’s
X5
Multiplier
125 MHz
20.833 Hz
5 - 8 January 2009
National Radio Science Meetings
77
Auxilary Slides
Digitizer Clock Module
5 - 8 January 2009
National Radio Science Meetings
78
Auxilary Slides
Digitizer Clock Assembly
IRAM, Grenoble
5 - 8 January 2009
National Radio Science Meetings
79
Auxilary Slides
Fiber Optic Multiplexer
Jodrell Bank Observatory
5 - 8 January 2009
National Radio Science Meetings
80
Auxilary Slides
Fiber Optic Amplifier / Demultiplexer
5 - 8 January 2009
National Radio Science Meetings
81
Auxilary Slides
Transmitter Module – Internal View
Digitizers
Backplane
Formatter
Monitor Control &
Power Supply
5 - 8 January 2009
National Radio Science Meetings
82
Auxilary Slides
DTS Test Stand
• “Golden” Modules
– 2 Data Transmitters
– 1 Digitizer Clock
– 2 Data Receivers
• Support Electronics
– PC with LabView
Interface
– System timing
– Data Receiver
backplane
5 - 8 January 2009
National Radio Science Meetings
83
Things We’d Do Differently …
• Single FPGA per channel!
– FPGA logic timing is difficult
– Economics will likely catch up
5 - 8 January 2009
National Radio Science Meetings
84
Things We’d Do Differently …
• Single FPGA per channel!
– FPGA logic timing is difficult
– Economics will likely catch up
• Closer interaction between hardware and firmware
designers
– Each should be the other’s backup
5 - 8 January 2009
National Radio Science Meetings
85
Things We’d Do Differently …
• Single FPGA per channel!
– FPGA logic timing is difficult
– Economics will likely catch up
• Closer interaction between hardware and firmware
designers
– Each should be the other’s backup
• Invite external expert’s opinions sooner during the
design process
5 - 8 January 2009
National Radio Science Meetings
86
Things We’d Do Differently …
• Single FPGA per channel!
– FPGA logic timing is difficult
– Economics will likely catch up
• Closer interaction between hardware and firmware
designers
– Each should be the other’s backup
• Invite external expert’s opinions sooner during the
design process
• Test Stand
– Design and build once assembly form factors are determined
5 - 8 January 2009
National Radio Science Meetings
87