Transcript Integrating Physical Test into the IC Studio Workflow Harry Peterson

Integrating Physical Test into the IC
Studio Workflow
Harry Peterson
Senior Director of IC Technology
Pixelworks Inc
Co-authors:
Angus Tang
Marc Ranger
Introduction
■
Trends:
—
—
—
—
—
—
■
What we can build is limited by our ability to manage
complexity
Co-design is everywhere
Schedules keep shrinking
Interaction among disciplines becomes tighter
Simulators are more powerful
ATE becomes relatively more expensive
Focus of this presentation:
—
Methodology for co-design of test program and mixedsignal chip
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Objective:
Minimize Time to (Profitable) Revenue
■
■
We must produce first-time-right mixed-signal
designs that are testable and cost-effective.
At the same time, we must deliver first-timeright test capability that is comprehensive
and cost-effective.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
The Idea
■
Create two views for the testbench:
Virtual
— Physical
—
■
By making it easy to flip between these two
representations, we speed up the
development and verification of mixed-signal
test programs.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Methodology
■
■
■
Instantiate both the physical and virtual view
of the testbench.
Create a pipe between these views.
Use views interchangeably in order to
validate and optimize both.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Testbench, in the virtual world
■
Resources for generating stimuli:
Dozens of types of signal generators exist
— For this session, we just look at PWL and
PULSE
—
■
Resources for analyzing responses:
EZWave
— Third-party (Kimotion) software mines data so
that we can automate regression tests
— Custom scripts bridge the gap between
Simulation software and ATE software
—
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Testbench, in the real (ATE) world
■
Resources for generating stimuli:
—
—
—
■
Resources for analyzing responses:
—
—
■
AWG (Arbitrary Waveform Generator)
Pin Driver
Other
Waveform digitizer
Comparator
Other resources:
—
—
Active load
Active and passive circuits on load board or probe card
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
EDA Tool Selection
■
Why we chose ADMS:
Allows us to efficiently move between accurate
transistor-level analysis and fast top-level
analysis.
— Efficient
—
■
Why we chose IC studio:
Good schematic-capture
— Gracefully accommodates a variety of other
views and resources
— Open
—
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
ATE Resource Selection
■
Credence D10
Powerful mixed-signal capability
— Good analog performance
— Open C++ style programming interface
— Well-suited to characterization as well as to
production testing
— Low cost
—
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Test Generation Methodology / Digital
■
■
Digital designers figured this out long ago.
But their problem was simpler:
—
■
Simply translate simulation data files into test
vectors for ATE tester
Examples of such vector translation tools:
VTRAN
— V2SCO
—
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Test Generation Methodology (Mixed-signal)
■
■
■
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Transfer of simulation data to tester program is
largely a manual process.
We need a more automatic transfer mechanism.
The concepts have been considered, but have not yet
been widely integrated into the workflow.
References:
—
—
[1] Viekko Loukusa. “Behavioral Test Generation Modeling
Approach for Mixed-signal IC Verification,” Proceedings of
International Mixed-Signal Testing Workshop 2002
[2] Geert Seuren, et al, “Extending the Digital Core-Based
Test Methodology to Support Mixed-Signal,” Proceedings of
International Test Conference, 2004
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Enabling technology for mixed-signal test
ICStudio
■ An integrated, user-friendly environment
■ Create, manage, and simulate design at
different levels of abstractions (Spice,
schematics, HDL)
■ Facilitates behavioral modeling and mixedlevel simulation
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Approach
■
■
■
Create top-level testbench to verify design in
simulation.
Top-level simulation is made possible
through the use of behavioral models.
The test bench is then used to generate the
main components of the ATE test program,
these includes the test vectors and tester
instrument setups.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Case Study: video AFE
■
Consists of the following blocks:
—
Signal pre-conditioning
■
■
■
—
Three fast ADCs
■
■
—
Input buffers
Clamps
Gain/Offset DAC
10-bit resolution
162MSPS
Timing recovery circuit
■
Line-locked PLL
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
DUT and the Simulation Testbench /1
Digital stimulus
Verilog
ADC
under
Test
Analog stimulus
Spice & Verilog AMS
Verilog AMS
t
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Monitors
DUT and the Simulation Testbench /2
■
The top-level testbench allows us to characterize the
ADC and extract important performance parameters
such as INL, DNL, and ENOB.
Digital stimulus
Verilog
ADC
under
Test
Analog stimulus
Spice & Verilog AMS
Verilog AMS
t
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Monitors
DUT and the Simulation Testbench /3
■
■
The digital stimulus block generates the
necessary clock and control signals to the ADC.
Digital stimuli are implemented as a Verilog
block.
Digital stimulus
Verilog
ADC
under
Test
Analog stimulus
Verilog AMS
t
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Spice & Verilog AMS
Monitors
DUT and the Simulation Testbench /4
■
The analog stimulus block generates a ramp
signal so that the output of the ADC can be
measured for linearity. Analog stimuli are
modeled behaviorally in Verilog AMS.
Digital stimulus
Verilog
ADC
under
Test
Analog stimulus
Spice & Verilog AMS
Verilog AMS
t
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Monitors
Case Study: video AFE
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Mapping the simulation testbench
to the ATE testbench /1
■
■
The digital stimuli are translated into test
vectors in ATE tester format.
The digital module of the D10 tester accepts
test vectors in STIL format, which can be
readily generated from simulation.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Mapping the simulation testbench
to the ATE testbench /2
Test_Bench_behavioral.va
.
.
.
//ramp input
module single_ended_ramp (.amplitude(1.0), .offset(0.5)...) Ramp(Rin_0, VSSA);
.
.
.
Top-level Test Bench
Analog stimulus
Verilog AMS
v
t
ADC_Test.cpp
.
.
.
void AWG_setup(double amplitude, double offset, string signal...)
{
/*********************************** AWG SETUP ***************************************/
.
.
cscTester->AWG()->Signal(signal)->OutputCtrl()->setOptimization(OPTIMIZE_FOR_NOISE);
cscTester->AWG()->Signal(signal)->OutputCtrl()->setAmplitude(amplitude);
cscTester->AWG()->Signal(signal)->OutputCtrl()->setCommonOffset(offset);
cscTester->AWG()->Signal(signal)->OutputCtrl()->setClockFrequency(awg_freq);
cscTester->AWG()->Signal(signal)->WaveformCtrl()->setSource(AWG_WAVEFORM_MEMORY);
cscTester->AWG()->Signal(signal)->WaveformCtrl()->setActiveWaveform(wfid);
cscTester->AWG()->Signal(signal)->WaveformCtrl()->setWaveformRepeat(ULONG_MAX);
.
.
}
.
.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Sapphire D-10
AWG
Mapping the simulation testbench
to the ATE testbench /3
■
■
■
Using the method described, the bulk of the
ATE test program can be generated from the
simulation testbench, before first silicon is
available.
Test program development time and effort is
reduced.
This flow bridges the communication gap
between test engineers and designers.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Next steps
■
■
■
■
1. Integrate the Kimotion ‘Breaker’ tool into this flow,
in order to more tightly close the loop between
‘executable spec’ and verified Silicon.
2. Adopt Mentor ‘Checkerboard’ tool in order to gain
the efficiency and quality benefits of greater
automation and faster simulation.
3. Pull software development and validation into the
co-design and product-verification loops.
4. Integrate Yield Analysis and Product Engineering
capabilities.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Next steps /1
Use Kimotion ‘Breaker’ tool to help mine simulation data
so we can make specs more executable
Design variables
■
■
Specifications
User-defined
testbenches measure
important circuit
performances
Breaker exercises
testbenches to find
most likely and/or
worst-case violations
for each performance
Performance models
Process and Environment
Eldo
KtModels
AdvanceMS
…
Optimized netlist
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Specification corners
Next steps /2
Use Mentor ‘Checkerboard’ tool to greatly improve speed
and effectiveness of chip-level simulation
Verification engineer traditionally has access to two types of block descriptions
■
.
Transistor-accurate netlists
slow, but capture all effects
Ideal behavioral models are fast, but
modeling extra effects requires tuning
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.param cload=2.5p
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l={l2} w={w2} m={min} l={l2} w={w2} m={min}
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outn reg
ref
l={l6} w={w6} m={mout}
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Checkerboard verification avoids the need for full spice simulation
vdd
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
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l={l4} w={w4} m={mout}
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l={l2} w={w2} m={min} l={l2} w={w2} m={min}
vss
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{cgbn}
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vss
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Captures impact of
block’s effects
on system behavior
m5b
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vdd biasgbp
vss casgbp
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biasn
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out biasgbn
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{ccm}
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l={l1} w={w1} m={min}
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vss
n2a
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l={l2} w={w2} m={min} l={l2} w={w2} m={min}
vss
vss
m2b
m2a
inp
biasn2
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
m3b
biasp
caspa
outp
C2
{cload} {cload}
vss
outp X7
outn reg
ref
{cgbn}
vss
l={l6} w={w6} m={mout}
m6b
Does not capture
interactions
Next steps /3
Pull software development and validation
into this codesign loop
■
■
In the virtual world: tools already support this.
In fact, a few people have been doing this (with huge
success) for about twenty years.
—
■
In the physical world: ATE resources to support this flow
have been widely available for only about two years.
—
—
■
Example: Andy Bechtolsheim’s team at Sun ran code and
booted the Sparc 1 chipset before they actually taped it out.
Example: D10 (Credence)
Trend: Open ATE initiative is gaining mainstream support
reference:
http://www.semitest.org/news/articles/FF_19_Yuhai_Ma_05.pdf
The bottom line: for many products, it is possible to do
validation (including software validation) at probe test. This
speeds up development schedules.
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Next steps /4
Integrate yield-analysis and
product-engineering capabilities
■
Yield Analysis Options
1.
Corners Analysis
■
■
■
1.
Classic Monte Carlo Analysis
■
■
■
2.
Corners are based on digital performance criteria
Requires many simulations
Leads to overdesign – more so with newer processes
Best accuracy
No overdesign
Requires a prohibitive number of simulations
Monte-Carlo with KtModel Analysis
■
■
■
Requires a limited number of simulations (user controlled)
Model evaluations replace simulation in monte-carlo loop
No overdesign
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Next steps /4
Integrate yield-analysis and
product-engineering capabilities
■
KtModeler improves
the accuracy of
behavioral models.
—
■
Behavioral
simulations can see
issues previously
caught only with spice
simulation.
KtModeler can also be
used instead of
simulator in montecarlo runs.
—
ADVance MS
V-AMS
Reduces the number
of simulations
required for montecarlo by 10-100x
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007
Spice
Fastspice
Verilog
Acknowledgements
■
Pixelworks executive support:
—
■
Pixelworks engineering team:
—
■
Sam Wasche, Christian Mayer, Brandon Barnes,
Vamsi Rachapudi
Credence:
—
■
Peter Lindholm
Mentor:
—
■
Jenkin Wong, Thomas Nasralla, Mike Parrish, Jay Sulima,
Pri Nallahandi, Liang Yuan
Insyte (ATE Consultant):
—
■
Hans Olsen
Ken Skala
Kimotion:
—
Bart De Smedt, Walter Daems
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HWP, Integrating Physical Test into the IC Studio Workflow, March 2007