Transcript Document 7802093

Chapter 6
Subprograms & Packages
Subprogram
declaration
Subprogram body
Package declaration
Package body
Resolution function
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Subprogram overloading
Subprogram return values
and types
Type casting and type
qualification
Exercises
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Subprogram declaration
Subprogram_declaration::=
procedure name[(interface_list)]|
function name[(interface_list)]
return type-mark;
VHDL Syntax (IEEE Std 1076-1987) check :
http://mikro.e-technik.uni-ulm.de/vhdl/vhdl87_syntax.html
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Subprogram declaration
interface_list::=interface_declaration{;interface_declaration}
interface_declaration::=
[constant] identifier_list:[in] subtype_indication
[:=static_expression]
[signal] identifier_list:[mode] subtype_indication[bus]
[:=static_expression]|
[variable] identifier_list:[mode]subtype_indication
[:=static_expression]
mode::=in|out|inout|buffer|linkage
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Subprogram declaration
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Subprogram body
Subprogram_body::=
subprogram_declaration is
subprogram_declarative_part
begin
sequential statements
end [procedure identifier or function designator];
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Subprogram body
entity FACT is
else
end FACT;
assert FALSE report "0 < N < 10 is not true"
architecture RTL of FACT is
severity NOTE;
function FACTORIAL (constant N :
return 0;
in integer) return integer is
end if;
begin
end FACTORIAL;
if (N = 1) then
signal NUM, RESULT : integer;
return 1;
begin
elsif (N > 1) and (N < 10) then
RESULT <= FACTORIAL (NUM);
return N * FACTORIAL (N - 1);
end RTL;
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Package declaration
Package_declaration::=
package identifier is
package_declarative_part
end[identifier];
Package declarative part may consist of subprogram
declaration, type, subtype, constant, signal, file, alias,
component, and attribute declarations, attribute and
disconnect specification, and use clause.
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Package declaration
package_body::=
package body identifier is
package_body_declarative_part
end[identifier];
Package body defines bodies of subprograms or values
of deferred constants declared in the package
declaration
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Package declaration
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package PACK1164 is
type std_ulogic is ( 'U',
-- Uninitialized
'X',
-- Forcing Unknown
'0',
-- Forcing 0
'1',
-- Forcing 1
'Z',
-- High
Impedance
'W',
-- Weak Unknown
'L',
-- Weak 0
'H',
-- Weak 1
'-');
-- Don't care
type std_ulogic_vector is array ( NATURAL RANGE <> ) of std_ulogic;
function resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
subtype UX01 is resolved std_ulogic RANGE 'U' TO '1';
subtype std_logic is resolved std_ulogic;
type std_logic_vector is array ( NATURAL RANGE <>) of std_logic;
function "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
function "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
function "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
end PACK1164;
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Resolution function
library IEEE;
use IEEE.std_logic_1164.all;
entity DRIVE2 is
port (
A, B, A_ENn, B_ENn : in std_logic;
Y
: out std_logic);
end DRIVE2;
architecture RTL of DRIVE2 is
begin
Y <= A when A_ENn = '0' else 'Z';
Y <= B when B_ENn = '0' else 'Z';
end RTL;
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Resolution function
package body PACK1164 is
type stdlogic_1d is array (std_ulogic) of std_ulogic;
type stdlogic_table is array (std_ulogic, std_ulogic)
of std_ulogic;
constant resolution_table : stdlogic_table := (
-- ---------------------------------------------------------- | U X 0 1 Z W L H | |
-- --------------------------------------------------------( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ),
-- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ),
-- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ),
-- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
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( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
function resolved ( s : std_ulogic_vector )
RETURN std_ulogic IS
variable result : std_ulogic := 'Z';
-- weakest state default
begin
if (s'LENGTH = 1) then
RETURN s(s'LOW);
else
for i in s'RANGE loop
result := resolution_table(result, s(i));
end loop;
end if;
RETURN result;
end resolved;
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Resolution function
architecture RTL of DRIVE2 is
begin
Y <= A when A_ENn = '0' else 'Z';
Y <= B when B_ENn = '0' else 'Z';
end RTL;
A
A_ENn
B
B_ENn
Y
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Notice that initial
drivers for Y are Z
---H---
--------L-------Z
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Subprogram overloading
constant and_table : stdlogic_table := (
-- ----------------------------------------------------- | U X 0 1 Z W L H | |
-- ---------------------------------------------------( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ),
-- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),
-- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ),
-- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),
-- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),
-- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),
-- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ),
-- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),
-- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )
-- | - |
);
function "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 is
begin
RETURN (and_table(l, r));
end "and";
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Subprogram overloading
Aliases are used to
normalize array bonds
function "and" (l,r : std_logic_vector )
RETURN std_logic_vector is
alias lv : std_logic_vector ( 1 TO l'LENGTH ) is l;
function "and" ( l,r : std_ulogic_vector )
alias rv : std_logic_vector ( 1 TO r'LENGTH ) is r;
RETURN std_ulogic_vector is
variable result : std_logic_vector ( 1 TO l'LENGTH );
alias lv : std_ulogic_vector ( 1 TO l'LENGTH ) is l;
begin
alias rv : std_ulogic_vector ( 1 TO r'LENGTH ) is r;
if ( l'LENGTH /= r'LENGTH ) then
variable result : std_ulogic_vector ( 1 TO l'LENGTH );
assert FALSE report
begin
"arguments of 'and' operator are not of the same length" if ( l'LENGTH /= r'LENGTH ) then
assert FALSE repor
severity FAILURE;
"arguments of 'and' operator are not of the same length"
else
severity FAILURE;
for i in result'RANGE loop
else
result(i) := and_table (lv(i), rv(i));
for i in result'RANGE loop
result(i) := and_table (lv(i), rv(i));
end loop;
end loop;
end if;
end if;
RETURN result;
RETURN result;
end "and";
end "and";
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EE514end PACK1164;
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Changed
from logic
to ulogic
Subprogram overloading
package SUBPROG is
procedure MUX21(
signal SEL : in bit;
signal DIN0 : in bit;
signal DIN1 : in bit;
signal DOUT : out bit);
procedure MUX21(
signal SEL : in bit;
signal DIN0 : in bit_vector;
signal DIN1 : in bit_vector;
signal DOUT : out bit_vector);
end SUBPROG;
package body SUBPROG is
procedure MUX21(
signal SEL : in bit;
signal DIN0 : in bit;
signal DIN1 : in bit;
signal DOUT : out bit) is
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begin
case SEL is
when '0' => DOUT <= DIN0;
when others => DOUT <= DIN1;
end case;
end MUX21;
procedure MUX21(
signal SEL : in bit;
signal DIN0 : in bit_vector;
signal DIN1 : in bit_vector;
signal DOUT : out bit_vector) is
begin
case SEL is
when '0' => DOUT <= DIN0;
when others => DOUT <= DIN1;
end case;
end MUX21;
end SUBPROG;
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Subprogram return values & types
library IEEE;
use IEEE.std_logic_1164.all;
entity SUBRETN is
signal A : std_logic_vector(7 downto 4);
signal B : std_logic_vector(0 to 3);
signal C : std_logic_vector(2 downto 0);
signal LB, RB, LA, RA : std_logic;
function INV (DIN : std_logic_vector) return
std_logic_vector is
variable result : std_logic_vector(1 to DIN'length);
begin
result := not DIN;
Errors- since range
return result;
does not match the
end INV;
end SUBRETN;
type of return value
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architecture RTL of SUBRETN is
begin
C <= INV(A)(2 to 4);
LA <= C(C'left);
RA <= C(C'right);
RB <= INV(B)(4);
LB <= INV(B)(1);
end RTL;
architecture ORDER of SUBRETN is
begin
C <= INV(A)(3 downto 1);
end ORDER;
architecture BOUND of SUBRETN is
begin
LB <= INV(A)(0);
end BOUND;
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Active CAD VHDL code window
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Simulation for RTL of SUBRETN
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Simulation for RTL of SUBRETN
architecture RTL of SUBRETN is
begin
C <= INV(A)(2 to 4);
LA <= C(C'left);
RA <= C(C'right);
RB <= INV(B)(4);
LB <= INV(B)(1);
end RTL;
A
1100
0101
1111
0001
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A’
0011
1010
0000
1110
C
011
010
000
110
LA
0
0
0
1
RA
1
0
0
0
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B
1100
0111
0011
0110
B’
0011
1000
1100
1001
RB
1
0
0
1
LB
0
1
1
1
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Type casting and type
qualification
Type UNSIGNED and operator “+” declared in
package std_logic_arith as follows
type UNSIGNED is array (NATURAL range <>)
of STD_LOGIC;
function “+” (L: UNSIGNED; R: USIGNED)
return STD_LOGIC_VECTOR;
type casting can convert types and requires
a single quote after type mark
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Type casting and type
qualification
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity CONVTYPE is
port (
RSTn, CLK : in std_logic;
CNTR4 : out std_logic_vector(3 downto 0));
end CONVTYPE;
architecture RTL of CONVTYPE is
signal CNTR4_FF : std_logic_vector(3 downto 0);
begin
CNTR4 <= CNTR4_FF;
p0 : process (RSTn, CLK)
begin
if (RSTn = '0') then
CNTR4_FF <= std_logic_vector'("0000");
elsif (CLK'event and CLK = '1') then
CNTR4_FF <= unsigned’(CNTR4_FF) + unsigned'("0001");
end if;
end process;
end RTL;
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