Transcript Document 7746225

Example
Loop:
L.D
F0, 0(R1)
Add.D
F0, F0, F2
S.D
0(R1), F0
L.D
F0, 0(R2)
Mult.D
F0, F0, F2
S.D
0(R2), F0
SUBI
R1, R1, 8
SUBI
R2, R2, 8
BNEZ
R2, Loop
•
Speculative Dynamic Machine specification
•
Issue rate of 1
•
One broadcast per cycle for CDB
•
branch takes 1 cycle,
•
Load takes 1 cycle,
•
integer alu takes 1 cycle,
•
float add takes 2 cycle
•
float multiply takes 3 cycle.
•
These cycle count doesn’t include write to CDB
Reorder buffer
Entry
Busy
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
Instruction
State
Destination
value
Cycle 0
Reservation table
Name
Busy
OP
Vj
Vk
Qj
Qk
Rob des
Add1
N
Loop: L.D F0, 0(R1)
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
N
Mult2
N
Int1
N
SUBI R1, R1, 8
Int2
N
SUBI R2, R2, 8
Int3
N
BNEZ R2, Loop
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
FP register status
Field
F0
f2
n
n
Reorder #
Busy
Reorder buffer
Entry
Busy
Instruction
State
Destination
value
1
Y
Ld f0, 0(R1)
issue
f0
Mem(R1)
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
Cycle 1
Reservation table
Name
Busy
OP
Vj
Vk
Qj
Qk
Rob des
Add1
N
Loop: L.D F0, 0(R1)
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
N
Mult2
N
Int1
Y
Int2
N
SUBI R2, R2, 8
Int3
N
BNEZ R2, Loop
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
ld
R1
#1
FP register status
Field
F0
Reorder #
#1
Busy
Y
f2
n
SUBI R1, R1, 8
Reorder buffer
Entry
Busy
Instruction
State
Destination
value
1
Y
Ld f0, 0(R1)
execute
F0
Mem(R1)
2
Y
Add.d f0 f0, f2
issue
F0
#1+F2
3
N
4
N
5
N
6
N
7
N
8
N
9
N
Cycle 2
Reservation table
Name
Busy
OP
Vj
Vk
Qj
f2
#1
Qk
Rob des
Add1
Y
addd
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
N
Mult2
N
Int1
Y
Int2
N
SUBI R2, R2, 8
Int3
N
BNEZ R2, Loop
#2
Loop: L.D F0, 0(R1)
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
ld
R1
#1
FP register status
Field
F0
Reorder #
#2
Busy
Y
f2
N
SUBI R1, R1, 8
Reorder buffer
Entry
Busy
Instruction
State
Destination
value
1
Y
Ld f0, 0(R1)
Write
F0
Mem(R1)
2
Y
Add.d f0 f0, f2
Excute
F0
#1+F2
3
Y
S.D 0(R1), F0
issue
4
N
5
N
6
N
7
N
8
N
9
N
Cycle 3
Reservation table
Name
Busy
OP
Vj
Vk
Qj
f2
#1
Qk
Rob des
Add1
Y
addd
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
N
Mult2
N
Int1
Y
ld
R1
Int2
Y
sd
R1
Int3
N
#2
Loop: L.D F0, 0(R1)
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
#1
#2
SUBI R1, R1, 8
SUBI R2, R2, 8
BNEZ R2, Loop
FP register status
Field
F0
Reorder #
#2
Busy
Y
f2
N
Reorder buffer
Entry
Busy
Instruction
State
Destination
value
1
N
Ld f0, 0(R1)
commit
F0
Mem(R1)
2
Y
Add.d f0 f0, f2
Excute
F0
#1+F2
3
Y
S.D 0(R1), F0
Excute
4
Y
L.D F0, 0(R2)
Issue
F0
Mem(R2)
5
N
6
N
7
N
8
N
9
N
Cycle 4
Reservation table
Name
Busy
OP
Vj
Vk
Qj
Qk
Rob des
Add1
Y
addd
f0
f2
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
N
Mult2
N
Int1
N
ld
R1
Int2
Y
sd
R1
Int3
Y
ld
R2
#2
Loop: L.D F0, 0(R1)
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
#1
Field
F0
Reorder #
#4
Busy
Y
SUBI R2, R2, 8
#2
#4
FP register status
f2
N
SUBI R1, R1, 8
BNEZ R2, Loop
Reorder buffer
Entry
Busy
Instruction
State
Destination
value
1
N
Ld f0, 0(R1)
Commit
F0
Mem(R1)
2
N
Add.d f0 f0, f2
Commit
F0
#1+F2
3
N
S.D 0(R1), F0
Commit
4
N
L.D F0, 0(R2)
Commit
F0
Mem(R2)
5
Y
Mult.D F0, F0, F2
Write
F0
6
Y
S.D 0(R2), F0
execute
7
Y
SUBI R1, R1, 8
Execute
R1
R1+8
8
Y
SUBI R2, R2, 8
execute
R2
R2+8
9
Y
Bnez r1, loop
Issue
Cycle n
Reservation table
Name
Busy
OP
Vj
Add1
N
Loop: L.D F0, 0(R1)
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
Y
Mult2
N
Int1
Y
sd
r2
Int2
Y
Subi
Int3
Y
subi
Multd
f0
Vk
Qj
Qk
f2
Rob des
#5
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
#5
#6
SUBI R1, R1, 8
R1
#7
SUBI R2, R2, 8
r2
#8
BNEZ R2, Loop
FP register status
Field
F0
Reorder #
#5
Busy
Y
f2
N
Reorder buffer
Entry
Busy
Instruction
State
Destination
value
1
N
Ld f0, 0(R1)
issue
F0
Mem(R1)
2
N
Add.d f0 f0, f2
Commit
F0
#1+F2
3
N
S.D 0(R1), F0
Commit
4
N
L.D F0, 0(R2)
Commit
F0
Mem(R2)
5
N
Mult.D F0, F0, F2
commit
F0
F0*F2
6
Y
S.D 0(R2), F0
execute
7
Y
SUBI R1, R1, 8
write
R1
R1+8
8
Y
SUBI R2, R2, 8
execute
R2
R2+8
9
Y
Bnez r1, loop
Issue
Cycle
n+1
Reservation table
Name
Busy
OP
Vj
Add1
N
Loop: L.D F0, 0(R1)
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
N
Mult2
N
Int1
Y
sd
r2
Int2
Y
Subi
Int3
Y
subi
Multd
f0
Vk
Qj
f2
Qk
Rob des
#5
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
f0
#6
SUBI R1, R1, 8
R1
#7
SUBI R2, R2, 8
r2
#8
BNEZ R2, Loop
FP register status
Field
F0
f2
N
N
Reorder #
Busy
Reorder buffer
Entry
Busy
Instruction
State
Destination
value
1
Y
Ld f0, 0(R1)
issue
F0
Mem(R1)
2
N
Add.d f0 f0, f2
Commit
F0
#1+F2
3
N
S.D 0(R1), F0
Commit
4
N
L.D F0, 0(R2)
Commit
F0
Mem(R2)
5
N
Mult.D F0, F0, F2
commit
F0
F0*F2
6
N
S.D 0(R2), F0
commit
7
Y
SUBI R1, R1, 8
Done write
R1
R1+8
8
Y
SUBI R2, R2, 8
write
R2
R2+8
9
Y
Bnez r1, loop
Issue
Cycle
n+2
Reservation table
Name
Busy
OP
Vj
Add1
N
Loop: L.D F0, 0(R1)
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
N
Mult2
N
Int1
Y
ld
r1
#1
SUBI R1, R1, 8
Int2
N
Subi
R1
#7
SUBI R2, R2, 8
Int3
Y
subi
r2
#8
BNEZ R2, Loop
Multd
f0
Vk
Qj
f2
Qk
Rob des
#5
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
FP register status
Field
F0
Reorder #
#1
Busy
Y
f2
N
Reorder buffer
Entry
Busy
Instruction
State
Destination
value
1
Y
Ld f0, 0(R1)
issue
F0
Mem(R1)
2
N
Add.d f0 f0, f2
Commit
F0
#1+F2
3
N
S.D 0(R1), F0
Commit
4
N
L.D F0, 0(R2)
Commit
F0
Mem(R2)
5
N
Mult.D F0, F0, F2
commit
F0
F0*F2
6
N
S.D 0(R2), F0
commit
7
Y
SUBI R1, R1, 8
Execute
R1
R1+8
8
Y
SUBI R2, R2, 8
execute
R2
R2+8
9
Y
Bnez r1, loop
Issue
Cycle
n+3
Reservation table
Name
Busy
OP
Vj
Add1
N
Loop: L.D F0, 0(R1)
Add2
N
Add.D F0, F0, F2
Add3
N
S.D 0(R1), F0
Mult1
N
Mult2
N
Int1
Y
ld
Int2
Y
Subi
Int3
Y
subi
Multd
f0
Vk
Qj
f2
Qk
Rob des
#5
L.D F0, 0(R2)
Mult.D F0, F0, F2
S.D 0(R2), F0
r1
#1
SUBI R1, R1, 8
R1
#7
SUBI R2, R2, 8
r2
#8
BNEZ R1, Loop
FP register status
Field
F0
Reorder #
#1
Busy
Y
f2
N
VLIW example
Loop:
L.D
F0, 0(R1)
Add.D
F0, F0, F2
S.D
0(R1), F0
L.D
F0, 0(R2)
Mult.D
F0, F0, F2
S.D
0(R2), F0
SUBI
R1, R1, 8
SUBI
R2, R2, 8
BNEZ
R2, Loop
•Static machine specification
•One delay slot between any
true data flow dependency
•One branch delay slot
Register rename
Loop:
L.D
F0, 0(R1)
Add.D
F0, F0, F2
S.D
0(R1), F0
L.D
F0, 0(R2)
Mult.D
F0, F0, F2
S.D
0(R2), F0
SUBI
R1, R1, 8
SUBI
R2, R2, 8
BNEZ
R2, Loop
Loop:
L.D
F0, 0(R1)
Add.D
F0, F0, F2
S.D
0(R1), F0
L.D
F1, 0(R2)
Mult.D
F1, F1, F2
S.D
0(R2), F1
SUBI
R1, R1, 8
SUBI
R2, R2, 8
BNEZ
R2, Loop
Instruction reorder
Loop:
L.D
F0, 0(R1)
Add.D
F0, F0, F2
S.D
Loop:
L.D
F0, 0(R1)
0(R1), F0
L.D
Add.D
F1, 0(R2)
F0, F0, F2
L.D
F1, 0(R2)
Mult.D
F1, F1, F2
Mult.D
F1, F1, F2
S.D
0(R1), F0
S.D
0(R2), F1
S.D
0(R2), F1
SUBI
R1, R1, 8
SUBI
R2, R2, 8
SUBI
BNEZ
SUBI
R2, R2, 8
R2, Loop
R1, R1, 8
BNEZ
R2, Loop
Software pipeline
L.D
F0, 0(R1)
L.D
F1, 0(R2)
L.D
F0, 0(R1)
Add.D
F0, F0, F2
L.D
F1, 0(R2)
Mult.D
F1, F1, F2
Add.D
F0, F0, F2
S.D
0(R1), F0
Mult.D
F1, F1, F2
S.D
0(R2), F1
S.D
0(R1), F0
SUBI
R2, R2, 8
S.D
0(R2), F1
SUBI
R1, R1, 8
SUBI
R2, R2, 8
SUBI
R1, R1, 8
BNEZ
R2, Loop
BNEZ
R2, Loop
8 copies
Code for one iteration.
L.D
F0, 0(R1)
L.D
F1, 0(R2)
Add.D
F0, F0, F2
Mult.D
F1, F1, F2
S.D
0(R1), F0
S.D
0(R2), F1
SUBI
R2, R2, 8
SUBI
R1, R1, 8
BNEZ
R2, Loop