Transcript 396-ps 32-bit Han-Carlson ALU in 180nm TSMC process Liang-Kai Wang VLSI CAD Lab

396-ps 32-bit Han-Carlson ALU
in 180nm TSMC process
Liang-Kai Wang
VLSI CAD Lab
University of Wisconsin, Madison
2016/5/26
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Outline
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Review of Adders
The Idea of Han-Carlson Adder
The Implementation of HanCarlson Adder
Simulation Result
Discussion
Comparison between Ling’s and
H-C Adder
Future work
Reference
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Review of Adders

Carry Ripple Adder
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Review of Adders(cont.)
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Carry Skip Adder
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Review of Adders(cont.)
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Carry-Select Adder
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Review of Adders(cont.)
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Carry-Save Adder
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Review of Adders(cont.)
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Carry Lookahead Adder
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Review of Adders(cont.)
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Ling Adder
gi  ai bi
pi  ai  bi
H1  g 7  g 6  p6 g5  p6 p5 g 4
ti  gi  pi (transfersignal)
Observation:
gi  pi gi
s7  t7  c7
c7  G1  P1G0
H 0  g3  g 2  p2 g1  p2 p1g 0
P6:3  p6 p5 p4 p3
h8  H1  P6:3 H 0 (Psudo Carry)
c7  p7 h8
 s 7  t 6  ( p7 h8 )
G1  G7:4  g 7  p7 g 6  p7 p6 g5  p7 p6 p5 g 4
 p7 ( g 7  g 6  p6 g5  p6 p5 g 4 )
G0  G3:0  g3  p3 g 2  p3 p2 g1  p3 p2 p1g 0
 p3 (g3  g 2  p 2g1  p 2p1g 0 )
P1  P7:4  p7 p6 p5 p4
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Back
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Review of Adders(cont.)
 Hybrid
(Parallel) Prefix Adder
Brent-Kung Adder
Kogge-Stone
Han-Carlson Adder
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Review of Adders(cont.)
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Brent-Kung Adder
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Cost : C(k)=C(k/2)+k-1=2k-2-log2k (# of adder
cells)
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Time : 2*log2k – 2 (in terms of adder levels)
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Review of Adders(cont.)
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Kogge-Stone Adder
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Cost : klog2k-(k-1)
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Time : log2k
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The idea of Han-Carlson Adder
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Han-Carlson Adder
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B-K adder: small area, but slow
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K-S adder: large area, but fast
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Speed: 2log2n-2log2n (1/2 reduction)
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Cost: 2k-2-log2kklog2k-k+1 (log2k/2 increase)
The area-time tradeoff results in HanCarlson Adder
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The idea of Han-Carlson Adder
(cont.)
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Han-Carlson Adder
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Cost : O(k/2*log2k)
Time : O(log2k+1)
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Review of Adders(cont.)
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Optimized Brent-Kung Adder
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Cost : C(k)=C(k/2)+k-1=2k-2-log2k
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Time : log2k (in terms of adder levels)
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The idea of Han-Carlson Adder
(cont.)
B-K
original
K-S
B-K
Optimal
H-C
Cost 2k-2-log2k klog2k-(k-1) 2k-2-log2k k/2*log2k
Delay 2*log2k – 2
Max. FO
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2
log2k
log2k
2
4
log2k+1
2
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The idea of Han-Carlson Adder
(cont.)
Produce Generate, Propagate, and Partial
Sum bit in the first stage.
 Single-rail circuit with double-rail in the
last stage to perform XOR function.
Sum=Partial_Sum XOR CarryIn
 Improved: Domino circuit with odd
stage in Dynamic and even stage in
Static.
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The implementation of HanCarlson Adder
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Schematics Design by Composer, Simulation by
Spectre. Both of them are in the Cadence design
kits
The simulation result is from Schematic (prelayout)
The best speed is achieved by using the fast mode
in the technology file instead of tuning the Bulk
voltage
Clock is generated by ring oscillator with five
inverters in the loop.
Cadence tutorial for both of them and about how
to setup the environment are provided here.
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The implementation of HanCarlson Adder(cont.)
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Clock generation:
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Ring Oscillator : five inverters followed by
lots of buffers
output
trigger
NMOS
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The implementation of HanCarlson Adder(cont.)
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Clock distribution
PG gen.
S0
S1
S2
S3
S4
stclk3
stclk2
Sum.
Sum#
Ø1
Sum gen.
Ø2
Correct
Latch
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The implementation of HanCarlson Adder(cont.)
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The whole view
A B Carry In
Path for P and G bit
PG gen.
CM0 CM1 CM2 CM3 CM4
M1
Foot-transistor
added
M2
Path for Psum bit
Correct
Sum
Sum #
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Sum gen.
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The implementation of HanCarlson Adder(cont.)
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ALU PG/Partial Sum Circuit.
Psum  A  B  AB  AB  ( A  B)( A  B)  PG
Back
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The implementation of
Han-Carlson Adder (cont.)
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Dynamic and Static Carry Merge Stage :

 i=0, 2,…30
G  Gi  Pi  Gi 1 
P  Pi  Pi 1
Even Stage :
Odd Stage:
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P  Pi 

G  Gi 
i=1, 3, … 31, or the carry at
that bit is already got.


P  Pi  Pi 1
 i  0, 2, ..., 30
G  Gi ( Pi  Gi 1 ) 


P  Pi 
 i  1, 3, ...,31
G  Gi 

or the carry at that bit is acquired
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Dynamic and Static Carry
Merge Stage (cont.):
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Carry-In of LSB should be
merged in order to do
subtraction.
The generate and propagate bit
MSB are passed to the last
stage to produce the carry_out
of the ALU. (for the check bit)
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The implementation of
Han-Carlson Adder (cont.)
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Even/Odd-bits CSG Sum
Generation
Complementary
signal generator
(CSG) logic
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The implementation of HanCarlson Adder (cont.)
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Even/Odd-bits CSG Sum Generation
 Use a latch to increase noise tolerance
Carry_bar
Carry
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Simulation Result
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Try the worst case pattern to test this design:
 A=0, B=-2, Carry-In=1 is the worst case delay.
 Why? Because from the structure of the circuit,
the worst case is 3N-2P-2N-2P-2N-2P-3N (For
Propagate bit)
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Simulation Result (cont.)
0th
stage: Carry-In=1
1st
stage: g=0, p=0, Psum=0 (P/G/Psum, 3N)
2nd
stage: g# =1, p# =1 (Static, 2P)
3rd stage: g=0, p=0 (Dynamic, 2N)
4th stage: g# =1, p# =1 (Static, 2P)
5th Stage: g=0, p=0 (Dynamic, 2N)
6th
stage: g# =1, p# =1 (static, 2P)
7th stage: Cin31=0, (Dynamic, 3N)
The
result should be “2” Correct = 1
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Simulation Result (cont.)
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Simulation Result (cont.)
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The result window
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Simulation Result (cont.)
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Test if the error flag is correct.
1st Test pattern: A=-231 B=-1.
The answer is 231-1
(1’b0+31’b1), which is the
wrong answer. And the correct
bit should be equal to 0. (test
the lower bound)
Also check the clock period is
about 396.23ps
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Simulation Result (cont.)
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Simulation Result (cont.)
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2nd Test pattern: A=231-1 B=2. The
answer is -231+1 (1’b1 +30’b 0+1’b1,
wrong answer), the correct bit should
be equal to 0. (test the upper bound)
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Simulation Result (cont.)
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Discussion: P/G/Psum Block
P circuit
G circuit
Psum circuit
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Mine
Psum= A xor B
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Discussion (cont.)
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What might be the problem?
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Longer path to the ground
When pre-charge, both of the propagate and
generate bit are “1”
What we need to consider? If p=0, g=0, this
circuit may have a good performance.
However, what if g goes from 1 to 0, but p=1?
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Discussion (Cont.)
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Discussion (cont.)
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If the longest path is cut, then…
Mine
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Discussion (Cont.)
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Mine
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Comparison between H-C
adder and Ling Adder
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Ling Adder:
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For n-bit Ling adder combining r groups
critical path:
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“logrn-1” levels
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r1 reduction result in logrn levels,
“-1” is because of the using of CLA expression rather than
Ling’s expression for the last group. Therefore, additional
stage is saved.
The worst case delay will remain the second path from the
last block
For each block, there are r+1 transistors serially
connected.
Use carry-select block for the generation of Sum bit. Only
additional “2” gate delays needed.
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Comparison between H-C
adder and Ling Adder(cont.)
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Lookahead Network
Td=(logrn-1)(r+1)+2
E.g. r=3, n=32, Td=14
CLA expression
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Group Generation
Carry-Select structure
(MUX)
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Comparison between H-C
adder and Ling Adder(cont.)
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H-C Adder:
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P, G generation =3
Carry Merge in each stage (including
dynamic and static) = 2
CSG Sum = 5
Td=2*log2n+3(P, G generation)+5 (CSG
Sum)
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E.g. n=32, Td=18
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Comparison between H-C
adder and Ling Adder(cont.)
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What is the pros and cons?
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Ling Adder:
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Advantage: shorter worse case path  might
be faster theoretically.
Disadvantage.:
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not regular layout Area waste
Lots of complex gates imply the charge sharing
problem.
Lots of input for a stage contribute to the long path
of wire  delay problem for high frequency
Carry-Select logic makes the area bigger.
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Comparison between H-C
adder and Ling Adder(cont.)
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Han-Carlson Adder:
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Disadvantage. : Longer path to the output
Advantage.:
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Regular layout for each stage
Fewer of inputs for each path imply the
resolution of interconnection
Simpler gates means few charge sharing
problem
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Future Work
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Power Reduction by inserting sleep transistors
Speed improvement by inserting discharge
transistors in the intermediate stack nodes of
the dynamic stages during precharge phase.
Area Reduction in layout
SOI model test
Self-Resetting to minimize the clock period
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Reference
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A 6.5GHz 130nm Single-Ended
Dynamic ALU and Instruction
Scheduler Loop, ISSCC 2002
Sub-500-ps 64-b ALUs in 0.18-um
SOI/Bulk CMOS: Design and
Scaling Trends, JSSC, Nov, 2001
Fast Area-Efficient VLSI Adders,
Proc. 8th Symp. Computer
Arithmetic, Sept. 1987
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Reference (cont.)
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Computer Arithmetic, Algorithms and Hardware
Design. Behrooz Parhami, Oxford University Press.
Advanced Computer Arithmetic Design. Michael J.
Flynn, et al. John Wiley & Sons, INC.
5 GHz 32b Integer-Execution Core in 130nm Dual-Vt
CMOS, ISSCC 2002
Implementation of a Self-Resetting CMOS 64-Bit
Parallel Adder with Enhanced Testability, JSSC Aug.
1999
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