Transcript Digital Design - Combinational Logic Design Chapter 2 - Combinational Logic Design

Digital Design - Combinational Logic
Design
Chapter 2 Combinational Logic Design
Digital Design
Combinational Logic Design
Motion a
sensor
Detector
F
Lamp
Light
sensor
b
(a)
Detector
I0
P0
uProc.
b
I1
a
(b)
a
Detector
F
F
b
(c)
Figure 2.1 Motion-in-the-dark-detector system: (a) system block diagram, (b)
implementation using a microprocessor, (c) implementation using a custom
digital circuit.
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Digital Design
4.5 A
Combinational Logic Design
- 9V+
2 ohms
0V
I = 9V/2 Ohms
I = 4.5 A
9V
V = IR
I = V/R
4.5 A
9V battery connected to light bulb
Ohms Law
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Digital Design
Combinational Logic Design
relay
tube
transistor
IC
quar ter (to see the relative size)
The evolution of switches:
•
Relays (1930s)
•
Vacuum tubes (1940s)
•
Discrete transistors (1950s)
•
Integrated circuit (IC) containing transistors (1960s--present).
IC’s originally held about ten transistors; now they can hold almost one billion.
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Digital Design
Combinational Logic Design
control
input
source
input
“off”
output
control
input
source
input
“on”
output
Figure 2.3 (b) Simple View of a Switch
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Digital Design
Combinational Logic Design
A positive
voltage here...
... attracts electrons here,
turning the channel
between source and drain
into a conductor.
gate
oxide
source
-
1
1
gate
1
1
0
1
conducts
pMOS
gate
drain
-
nMOS
does not
conduct
1
1
1
0
1
does not conducts
conduct
-
silicon
IC package
IC
Figure 2.4 CMOS transistors: (left) transistor on silicon, (right top) nMOS transistor symbol
with indication of conducting when gate=1, (right bottom) pMOS transistor symbol
conducts when gate=0
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Digital Design
Combinational Logic Design
gate
gate
source
drain
source
drain
Figure 2.5 CMOS transistor operation analogy -- Crossing a river may be too difficult,
until just enough stepping stones are attracted into one pathway
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Digital Design
Combinational Logic Design
Figure 2.6 Having the right building blocks can make all the difference when building things.
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Digital Design
Combinational Logic Design
NOT
x
OR
F
AND
x
x
F
y
x
0
0
1
1
x F
0 1
1 0
1
y
0
1
0
1
F
0
x y
0 0
0 1
1 0
1 1
F
0
1
1
1
1
x
x
F
y
1
y
x
F
x
y
x
y
F
0
0
0
1
F
y
0
Figure 2.7 Basic logic gates.
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Digital Design
Combinational Logic Design
1
x 0
x
F
1
F0
time
NOT
1
0
1
y
0
F1
0
x
x
y
F
OR
time
x
y
1
0
1
y
0
F1
0
x
F
AND
Logic Gate
time
Behavior and Timing
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Digital Design
Combinational Logic Design
Inputs
k 1
0
1
s 0
k BeltWarn
w
s
Outputs
w1
0
Figure 2.11 Seatbelt Warning Circuit
time
Figure 2.11 Timing diagram for
seatbelt warning circuit
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Digital Design
Combinational Logic Design
k BeltWarn
p
w
s
k
p
s
BeltWarn
w
t
Figure 2.13 Seatbelt warning
circuit with person sensor.
Figure 2.14 Extended seatbelt
warning circuit.
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Digital Design
Combinational Logic Design
Commutative:
a + b = b + a
a * b = b * a
Distributive
a*(b + c) = a*b + a*c
a+(b * c) = (a+b) * (a+c)
Associative
(a + b) + c = a + (b + c)
(a * b) * c = a * (b * c)
Identity
0 + a = a + 0 = a
1 * a = a * 1 = a
Complement
a + a’ = 1
a * a’ = 0
Boolean Algebra – Basic Properties
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Digital Design
Combinational Logic Design
Null elements
a + 1 = 1
a * 0 = 0
Idempotent Law
a + a = a
a * a = a
Involution Law
(a’)’ = a
DeMorgan’s Law
(a + b)’ = a’b’
(ab)’ = a’ + b’
Boolean Algebra – Additional Properties
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Digital Design
Combinational Logic Design
Inputs
F = ab + a’
a=0
a=0
a=1
a=1
and b=0,
and b=1,
and b=0,
and b=1,
F
F
F
F
=
=
=
=
0*0
0*1
1*0
1*1
+
+
+
+
1
1
0
0
=
=
=
=
0
0
0
1
+
+
+
+
1
1
0
0
=
=
=
=
1
1
0
1
Outputs
a
b
F
0
0
1
0
1
1
1
0
0
1
1
1
Truth Table
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Digital Design
Combinational Logic Design
Inputs
P = a’b’c + a’bc’ + ab’c’ + abc
Outputs
a
b
c
P
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
Even Parity for Three-bit Generator
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Digital Design
Combinational Logic Design
a
b
e
d
g
a
b
c
d
e
f
g
c
f
abcdefg =
1110111
0010010
1011101
Figure 2.18 Seven-segment display (left), sample numbers 0, 1 and 2 (center),
and connections of inputs to segments (right)
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Digital Design
Combinational Logic Design
w
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
a
1
0
1
1
0
1
1
1
1
1
0
0
0
0
0
0
b
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
c
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
d
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
e
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0
f
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
g
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
Table 2.2 4-bit binary number to seven-segment display truth table
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Digital Design
Combinational Logic Design
Create a truth table or equations, whichever is most natural for
the given problem, to describe the desired behavior of the
combinational logic.
Convert to
equations
This step is only necessary if you captured the function using a
truth table instead of equations. Create an equation for each
output by ORing all the minterms for that output. Simplify the
equations if desired.
Implement
as a gatebased
circuit
For each output, create a circuit corresponding to the output’s
equation. (Sharing gates among multiple outputs is O.K.
optionally)
Step 1
Capture the
function
Step 2
Description
Step 3
Step
Combinational Logic Design Process
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Digital Design
Combinational Logic Design
Step 1: Capture the function
y = abc + bcd + cde + def + efg + fgh
Step 2: Convert to equations
Skip this as we have the equations.
Step 3: Implement as a gate-based circuit
b
c
d
abc
bcd
cde
y
e
def
f
efg
g
fgh
h
Three 1s pattern detector
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Digital Design
Combinational Logic Design
Step 1: Capture the function
a
0
0
0
0
1
1
1
1
Inputs
b
c
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
(# of 1s)
(0)
(1)
(1)
(2)
(1)
(2)
(2)
(3)
Outputs
y
z
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
Step 2: Convert to equations
y = a’bc + ab’c + abc’ + abc
z = a’b’c + a’bc’ + ab’c’ + abc
Number-of-1s counter gate-based circuit
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Digital Design
Combinational Logic Design
Step 3: Implement as a gate-based circuit
a
b
c
a
b
c
a
b
y
a
b
c
a
b
c
a
b
c
a
b
c
z
Number-of-1s counter gate-based circuit
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Digital Design
Combinational Logic Design
Microprocessor
d0
d1
d2
d3
d4
decoder d5
d6
e
d7
a
b
c
zone 0
zone 1
3
4
5
7
2
6
Figure 2.22 Sprinkler valve controller block diagram.
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Digital Design
Combinational Logic Design
Step 1: Capture the function
d0 = a’b’c’e
d1 = a’b’ce
d2 = a’bc’e
d3 = a’bce
d4 = ab’c’e
d5 = ab’ce
d6 = abc’e
d7 = abce
a
b
c
d0
d1
d2
d3
Step 2: Convert to equations
d4
Skip this as we have the equations.
d5
Step 3: Implement as a gate-based circuit
d6
d7
e
Sprinkler valve controller circuit (actually a 3x8 decoder with enable)
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Digital Design
Combinational Logic Design
NAND
NOR
x
y
F
x
XOR
XNOR
F
y
x y
0 0
0 1
1 0
1 1
F
1
1
1
0
x
0
0
1
1
1
x
y
F
x
y
x
y
y
0
1
0
1
1
y
0
1
0
1
F
0
1
1
0
x
0
0
1
1
y
0
1
0
1
F
1
0
0
1
F
y
x
0
x
0
0
1
1
F
1
0
0
0
0
Figure 2.24 NAND, NOR, XOR and XNOR
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Digital Design
Combinational Logic Design
d0
1
i0 d1 0
0
i1 d2
d3 0
d0
0
0
d0
0
1
0
d0
1
i0 d1 1
i1 d2 0
0
d3 0
0
i0 d1 0
i1 d2 1
d3 0
0
d1
i0 d1 0
i1 d2 0
d2
d0
1
1
d3 1
d3
(a)
i1
i0
(b)
Figure 2.25 2x4 decoder: (a) outputs for possible input combinations, (b) internal design
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Digital Design
Microprocessor
Combinational Logic Design
i0
i1
i2
i3
i4
i5
e
d0
d1
d2
d3
d58
d59
d60
d61
6x64 d62
dcd d63
0
Happy
New Year!
1
2
3
58
59
Figure 2.26 sing a 6x64 decoder to interface a microprocessor
and a column of lights for a New Year’s Eve display
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Digital Design
Combinational Logic Design
i0
d
i1
i2
0
i3
1 2
3
control lever
Figure 2.27 A multiplexer is like a railyard switch, determining which input track
connects to the single output track, according to the switch’s control lever.
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Digital Design
Combinational Logic Design
2x1
2x1
2x1
i0
i1 d
i0
i1 d
i0
i1 d
s0
s0
0
s0
i0
d
i1
1
s0
Figure 2.28 2x1 multiplexer block symbol (left), connections for
s0=0 and s0=1 (middle), and internal design (right).
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Digital Design
Combinational Logic Design
i0
4x1
i0
i1
d
i2
i2
i3
s1 s0
i3
i1
d
s1 s0
Figure 2.29 4x1 multiplexer block symbol (left) and internal design (right).
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Digital Design
Combinational Logic Design
Proposal
Mayor’s switches
1
4x1 on/off
i0
2
i1
d
i2
3
i3
Red
4
s1 s0
LED
switches
Figure 2.30 Mayor’s vote display system implemented using a 4x1 mux.
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Digital Design
Combinational Logic Design
a3
b3
i0 2x1
i1 s0d
c3
a2
b2
a1
b1
i0 2x1
i1 s0d
c2
i0 2x1
i1 s0d
c1
a0
b0
i0 2x1
i1 s0d
c0
A 4 i0 4-bit
2x1
B 4 i1
d
s0
4
C
s0
Figure 2.31 Four 2x1 muxes for selecting among 4-bit data items A or B (left), and a
simpler way to represent the same component using a 4-bit 2x1 mux component (right).
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Digital Design
Combinational Logic Design
i0 8-bit
4x1
i1
d
i2
i3 s1 s0
x
y
To the abovemirror display
T
A
I
M
D
button
Figure 2.32 Above-mirror display using an 8-bit 4x1 mux.
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Digital Design
Combinational Logic Design
Figure 2.33 Schematic for 2x4 drawn using a popular commercial schematic capture tool.
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Digital Design
Combinational Logic Design
Inputs
i0
i1
Outputs
d3
d2
d1
d0
Simulate
(a)
Inputs
i0
i1
Outputs
d3
d2
d1
d0
Simulate
(b)
Figure 2.34 Simulation: (a) begins with us defining the inputs signal over time,
(b) automatically generates the output waveforms when we ask the simulator to
simulate the circuit.
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Digital Design
Combinational Logic Design
F
y
1
0
1
y
0
F1
0
1
0
1
y
0
F1
0
x
x
(a)
time
(b) time
Figure 2.35 OR gate timing diagram: (a) without gate delay, (b) with gate delay.
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