Transcript Digital Design – Register-Transfer Level (RTL) Design Chapter 5 -

Digital Design – Register-Transfer Level
(RTL) Design
Chapter 5 Register-Transfer Level (RTL) Design
Digital Design
RTL Design
Step 1
Create a highlevel state
machine
Step 2
Describe the system’s desired behavior as a high-level state machine. The
state machine consists of states and transitions. The state machine is “highlevel” because the transition conditions and the state actions are more than
just Boolean operations on bit inputs and outputs. The operations may be
described in English (e.g., “turn on laser”) rather than as precise expressions
or assignments of inputs and outputs (e.g., “L=1”).
Create a
datapath
Create a datapath to carry out the conditions and actions of the high-level
state machine.
Step 3
Description
Connect the
datapath to a
controller
Connect the datapath to a controller block. Connect all external inputs and
outputs to either the controller block or the datapath block
Step 4
Step
Derive the
controller’s FSM
Convert the high-level state machine to a finite-state machine (FSM) of the
controller, by replacing high-level conditions and actions with Boolean
expressions and assignments involving actual controller inputs and outputs,
which cause transfers and operations in the datapath.
Table 5.1 RTL Design Process
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Digital Design
RTL Design
T (in seconds)
D
laser
object of
interest
sensor
2D = T sec * 3x108 m/sec
Figure 5.1 Laser-based distance measurement.
from button
to display
D
L
Laser-based
distance
measurer
to laser
from sensor
S
Figure 5.2 Block diagram of the laser-based distance measurement system.
Example 5.1 Laser-based distance measurer.
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Digital Design
RTL Design
Step 1: Create a high-level state machine
Inputs: B, S (bits)
Outputs: L (bit), D (16 bits)
button not pressed
reflection not detected
button
reflection
S0
S1
S2
S3
S4
S5
pressed
detected
turn on laser turn off laser
turn off laser
load Dreg with
clear Dreg clear timer enable timer
disable timer timer value converted
to meters
Example 5.1 Laser-based distance measurer.
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Digital Design
RTL Design
Step 2: Create a datapath
Datapath
Dreg_clr
Dreg_ld
Dctr_clr
Dctr_cnt
300 MHz clock
clear
count
Dctr: 16-bit
up-counter
Q
clear
load
I
Dreg: 16-bit
Q register
16
D
Example 5.1 Laser-based distance measurer.
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Digital Design
RTL Design
Step 3: Connect the datapath to a controller
from button
B
Controller
(Implemented
FSM of
Fig. 5.6)
D
to display
L to laser
S from sensor
Dreg_clr
Dreg_ld
Dctr_clr
Datapath
(Fig. 5.4)
Dctr_cnt
300 MHz Clock
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Digital Design
RTL Design
Step 4: Derive the controller’s FSM
Inputs: B, S
Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt
B=0
S0
S1
S=0
B=1
S2
S3
S=1
S4
L=0
L=0
L=0
L=1
L=0
Dreg_clr=1 Dreg_clr=0 Dreg_clr=0 Dreg_clr=0 Dreg_clr=0
Dreg_ld=0 Dreg_ld=0 Dreg_ld=0 Dreg_ld=0 Dreg_ld=0
Dctr_clr=0 Dctr_clr=1 Dctr_clr=0 Dctr_clr=0 Dctr_clr=0
Dctr_cnt=0 Dctr_cnt=0 Dctr_cnt=1 Dctr_cnt=1 Dctr_cnt=0
(turn off laser)(clear timer) (turn on laser)
(disable timer)
(clear Dreg)
(enable timer)
(turn off laser)
S5
L=0
Dreg_clr=0
Dreg_ld=1
Dctr_clr=0
Dctr_cnt=0
(load Dreg)
Example 5.1 Laser-based distance measurer.
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Digital Design
RTL Design
Inputs: B, S
Outputs : L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt
B=0
S0
S=0
S1
S3 S=1
S4
S5
B=1 S2
Dreg_clr=1 Dctr_clr=1
L=1
L=0
Dctr_cnt=0 Dreg_ld=1
(clear Dreg)(clear timer) Dctr_cnt=1 Dctr_cnt=1(disable timer) (load Dreg)
(turn on laser)(turn off laser)
(enable timer)
Figure 5.7 FSM description of the controller for the laser-based distance measurer,
using the convention that FSM outputs not explicitly assigned a value in a state
are implicitly assigned 0
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Digital Design
RTL Design
190
182
180
I
time
Basic
filter
Q
184
182
180
time
180 181 182 190 182 182 182 182
180 180 180 181 183 184 184 184 182
Figure 5.8 A basic digital filter that outputs the average of the previous four
inputs, assuming the input was steady at 180 for a long time before the above
sequence began, and stays at 182 for a long time after the sequence.
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Digital Design
RTL Design
cycle:
1
2
3
4
5
6
7
8
value on input I: 180 181 182 190 182 182 182 182
1
2
3
5
Ia
4
6
Ib
7
Ic
8
Id
Figure 5.9 Writing the four registers in a round-robin manner to always maintain
the previous four input values in the registers.
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Digital Design
RTL Design
I
8
Ia_ld
S0
Ia_l d=1
S1
Qreg_ld=1
S2
Ib_ld=1
Qreg_ld=1
Ireg_clr=1
Qreg_cl r=1
Id_ld=1
S4
Ib
Ic
Id
Ib_ld
Ic_ld
Id_ld
Ireg_clr
8-bit adder
Qreg_ld=1
8-bit adder
8-bit adder
>>2
S3
Ic_ld=1
Qreg_ld=1
Ia
Qreg_ld
Qreg_clr
Controller
Basic Filter
Qreg
8
Datapath
Q
Figure 5.10 Datapath (right) and FSM description of the controller (left) for our
basic filter.
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Digital Design
RTL Design
Inputs: rd (bit), Q (32 bits), A, Faddr (4 bits)
Outputs: D (32 bits)
Local register: Q1 (32 bits)
rd’
rd
((A=Faddr)
and rd)’
WaitMyAddress
SendData
(A=Faddr)
D=Q1
D = “Z”
and rd
Ql=Q
Figure 5.11 High-level state machine of the sending half of a simple bus
interface.
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Digital Design
RTL Design
clk
Inputs
rd
State
W W SD W
Outputs
D
Z
Q1
W
Z
SD SD W
Q1
Z
Figure 5.12 Bus interface timing diagram.
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Digital Design
RTL Design
Faddr Q
4 4
32
Ql
= (4-bit)
A
rd
rd’
rd
A_eq_Faddr
and rd)’
WaitMyAddress
D_en=0
Ql_ld=1
SendData
A_eq_Faddr D_en=1
and rd
Ql_ld=0
Controller
Ql_ld
A_eq_Faddr
D_en
Datapath
Bus interface
32
D
Figure 5.13 Datapath (right) and controller FSM description (left) for the simple
bus interface.
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Digital Design
RTL Design
Frame1
Frame2
Digitized frame1 Digitized frame2
1 Mbyte
1 Mbyte
Frame1
Frame2
Digitized frame1 Difference of 2 from 1
1 Mbyte
0.01 Mbyte
Figure 5.14 A key principle of video compression recognizes that successive
frames have much similarity.
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Digital Design
RTL Design
Inputs: A, B (256-byte memory), go (bit)
Outputs: sad (32 bits)
Local registers: sum, sad_reg (32 bits), i (9 bits)
B
go
SAD
sad
!(i<256)
A
!go
S0
go
sum=0
S1 i=0
S2
i<256
S3 sum=sum+abs(A[i]-B[i])
i=i+1
S4
sad_reg = sum
Figure 5.15 Sum-of-absolute-differences (SAD) component: block diagram (left),
and high-level state machine (right).
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Digital Design
RTL Design
!(i<256) !(i_lt_256)
go
AB_addr
AB_rd
!go
S0
go
sum=0 sum_clr=1
S1 i=0 i_clr=1
A_data B_data
i_lt_256<256
i_inc
-
i
i_clr
sum_ld
S2
i<256 i_lt_256
sum
sum_clr
S3 sum=sum+abs(A[i]-B[i])
sum_ld=1; AB_rd=1
i=i+1 i_inc=1
sad_reg_ld
S4 sad_reg = sum
sad_reg
sad_reg_ld=1
Controller Datapath
sad
abs
+
Figure 5.16 SAD datapath and controller FSM.
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Digital Design
RTL Design
1.5
original
1
0.5
noisy
fir_avg_out
0
-0.5
-1
-1.5
Figure 5.17 Results of a 5-tap FIR filter with c0=c1=c2=c3=c4=0.2 applied to a
noisy signal.
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Digital Design
RTL Design
2.5
in1
2
in2
1.5
in_total
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
Figure 5.18 Adding a main signal, in1, to a carrier signal, in2, resulting in a
composite signal in_total.
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Digital Design
RTL Design
2.5
2
1.5
in_total
fir_out
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
Figure 5.19 Filtering out the carrier signal using a 7-tap FIR filter with constants
0.25, 0, 0, 0.5, 0, 0, 0.25. The slight delay in the output signal typically poses no
problem.
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Digital Design
RTL Design
X
3-tap FIR filter
Y
clk
Figure 5.20 General block diagram of an FIR filter.
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Digital Design
RTL Design
x(t)
X
xt0
3-tap FIR filter
x(t-1)
x(t-2)
xt1
xt2
Y
clk
Figure 5.21 Beginning to build the datapath for the FIR filter -- inserting and
connecting the x(t), x(t-1) and x(t-2) registers.
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Digital Design
RTL Design
3-tap FIR filter
x(t)
X
xt0
c0
x(t-1)
xt1
c1
x(t-2)
c2
xt2
clk
Y
Figure 5.22 Extending the datapath for the FIR filter -- inserting and connecting
the c0, c1, and c2 registers, along with the multipliers, for each tap.
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Digital Design
RTL Design
3-tap FIR filter
x(t)
X
xt0
c0
x(t-1)
xt1
c1
x(t-2)
c2
xt2
clk
Y
Figure 5.23 Computing the output Y in the FIR filter as the sum of the tap
products.
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Digital Design
RTL Design
CL
Ca1
Ca0
3-tap FIR filter
e 3
2
2x4 1
0
C
x(t)
X
xt0
c0
x(t-1)
xt1
c1
x(t-2)
c2
xt2
clk
yreg
Y
Figure 5.24 Finalizing the FIR filter datapath with circuitry for loading the
constant registers.
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Digital Design
RTL Design
int SAD(byte A[256], byte B[256]) // not quite C syntax
{
uint sum; short uint i;
sum = 0;
i = 0;
while (i < 256) {
sum = sum + abs(A[i] - B[i]);
i = i + 1;
}
return(sum);
}
Figure 5.25 C program description of a sum-of-absolute differences computation - The C program may be easier to develop and easier to understand than a state
machine.
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Digital Design
RTL Design
!cond
target =
expression
target = expression;
if (cond) {
// then stmts
}
cond
(then stmts)
(end)
Figure 5.26 T for assignment statement.
Figure 5.27 Template for if-then statement.
!cond
!cond
if (cond) {
// then stmts
}
else {
// else stmts
}
cond
(then stmts) ( else stmts)
(end)
Figure 5.28 Template for if-then-else statement.
while (cond) {
// while stmts
}
cond
(while stmts)
(end)
Figure 5.29 Template for while loop statement.
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Digital Design
RTL Design
Inputs: uint X, Y
Outputs: uint Max
!(X>Y)
!(X>Y)
X>Y
X>Y
if (X > Y) {
Max = X;
}
else {
Max = Y;
}
(a)
(then stmts)
( else stmts)
Max=X
Max=Y
(end)
(end)
(b)
(c)
Figure 5.30 Behavioral-level design starting from C code.
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Digital Design
RTL Design
Inputs: byte A[256],B[256]
bit go;
Outputs: int sad
main()
{
uint sum; short uint i;
while (1) {
}
}
(a)
!(!go)
!go
!go
i=0
i=0
sum=0
i<256
go
!go
!(i<256)
!(i<256)
(d)
(c)
i=0
sum=0
i=0
go
!go
go
go
sum=0
sum=0
while (!go);
sum = 0;
(b)
i = 0;
while (i < 256) {
sum = sum + abs(A[i] - B[i]);
i = i + 1;
}
sad = sum;
!go
!go
go
i<256
sum = sum + abs...
i=0
while stmts
sum=0
i=0
!(i<256)
i<256
sum = sum + abs...
i=0
sad = sum
sad = sum
(e)
(f)
(g)
Figure 5.31 Behavioral-level design of the sum-of-absolute difference code.
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