Transcript PHENIX Silicon Endcap Physics p-p A-A p-A

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PHENIX Silicon Endcap Physics
p-p
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Open Charm Measurement
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ccm(displaced)X
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ccm(displaced)X
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Gerd J. Kunde
Open Beauty Measurement
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PHENIX Silicon Endcap
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 Executive Summary
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Four umbrella stations on each side
Mini-strips of 50mu * 2.2 -13 mm
Readout via new PHX chip from Fermilab
Data push via ~3 Gigabit optical links
Total channel count: 2 Million channels
Total chip count: 4000 chips
Gerd J. Kunde
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Si Vertex - Preliminary Design
Si-Umbrellas
Conceptual Integration
Design by LANL/Hytec
Gerd J. Kunde
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Si Umbrella Layout
Preliminary
7/03
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 50 mu radial pitch (z vertex reconstruction)
 2816 (2048) “mini-strips”
 3.5 cm < r < 18 (14) cm
 48 “double towers” in phi
 mini-strips from
2.2 mm to 13.0 mm
 2 rows of strips in one
“double tower”, readout by one chip
series
 4 half-towers in “wedge” (later slide)
 24 wedges in one “umbrella”
 2 * 4 umbrellas ( 22 degree tilt)
Gerd J. Kunde
2816
2048
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r = 18.0 cm
r = 14.0 cm
r = 3.5 cm
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Collaboration with FNAL
• Started to work with Ray Yarema’s group
– They did D0 and CDF silicon readout (SVX#)
– They developed Btev prototype (FPIX)
– Propose to build PHX, combine technologies …
– Did simulations for ministrips
– Produced preliminary chip layout
– Solved readout bus challenge
– Presented at PHENIX Nashville collaboration meeting
– Second round of discussions at FEE2003
• Displaced Vertex Trigger
– Propose to use FNAL infrastructure to prototype, test and
assemble chips and detectors
Gerd J. Kunde
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FPIX2 Features
• Advanced mixed
analog/digital design
• 128 rows x 22 columns
(2816 channels)
• 50 µm x 400 µm pixels
• High speed readout intended
for use in Level 1 trigger. Up
to 840 Mbits/sec data output.
• Very low noise
• Excellent threshold matching
• DC coupled input
• Fully programmable device
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Pixel Cells 50 x 400 um
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Vdda
Thresholds
Token Out
+
Flash
Vff
ADC
Thermometer
to Binary
Encoder
Latch
Resets
Row
Address
Bus
Sensor
-
Command Interpreter
+
00 - idle
01 - reset
10 - output
11 - listen
Kill
Inject
Controller
Test
Vref
Threshold
4 pairs of
Command Lines
RFastOR
Throttle
HFastOR
12 µm bump
pads
Preamp 2nd stage
+disc
ADC
Kill/
inject
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ADC
encoder
Read Clock
Read Reset
Token In
Token Reset
Digital interface
Ray Yarema, FNAL, June 9th
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FPIX2 Status
• Produced 3168 chips in engineering run
• Minor tweaking of design needed before production
• Mixed analog/digital design has excellent
performance with insignificant interference and cross
talk.
• Chip size is 8.96 mm x 10.2 mm (91 mm2)
• Yield is high
• Chip and readout can be used “as is” in other pixel
applications
Gerd J. Kunde
FPIX Measured Performance
from Prototype Run
FPIX2
Threshold
Distribution
@ Cin= 0 pf
is 125 erms
FPIX2 noise
at C = 0
is about
60 erms
Reminder: MIP in 300 mu Silicon gives 24,000 electrons !!!!
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Ray Yarema, FNAL, June 9th
Pixel/Strip Sizes
• FPIX
• Phenix
• SVX
50 x 400 um
50 x 2000 to 11000 um
50 x 105 to 3x105 um
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Cin = .25 pF
Cin = .2-1.1 pF?
Cin = 10-30 pF
Design for Phenix will be optimized for
correct detector capacitance
Gerd J. Kunde
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Ray Yarema, FNAL, June 9th
Bits and Pieces for Phenix Chip
PHX
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Use modified FPIX2 front end
Use relaxed bump bonding connections
Use pipeline* and sparcification concepts from SVX4
Use backside contact for ground return (as done in
SVX4)
• Use slow programming control from FPIX2
• May use modified output drivers from FPIX2
* rather data push from FPIX for trigger purposes
Gerd J. Kunde
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Ray Yarema, FNAL, June 9th
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First Simulations for Phenix at FNAL
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Simulated
FPIX2 first and
second stage
response for
detector
capacitances
from 0 to 2 pF in
0.25 pF steps
First stage
Second stage
Gerd J. Kunde
Ray Yarema, FNAL, June 9th
Possible Layout Diagram for PHX Chip
Bump bonds
Programming interface
1st and 2nd stage and discriminator
Pipeline
Digital interface
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signals & power
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PHX Chip Layout:
2 columns
256 channels/column
3.8 mm x 13 mm = 49.4 mm2
Bump bonds on 200 um pitch
50 µm dia bumps
512 bumps plus inter-chip bumps
for the bus
FPIX2 Layout for comparison:
Chip area = 91 mm2
Bump bonds on 50 µm pitch
12 µm dia bumps
2816 bumps
signals & power
Gerd J. Kunde
Ray Yarema, FNAL, June 9th
PHX: Possible Tower Section
Carbon Wedge Support and Cooling
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Only “2 ½” Silicon Detector types
Inside Detector (I)
5 chips= 2560 strips
Outside Detector (II)
6 chips= 3072 strips
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Outside Detector (III)
3 chips= 1536 strips
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Wedge Assembly Idea
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3 mm carbon wedge for
assembly and cooling
2 silicons in front
2 silicons in back
Reason: Eliminate dead silicon areas by overlapping 1 mm along edges ….
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From Wedges to Umbrellas
X 24
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Ray Yarema, FNAL, June 9th
Proposed PHX Design Plan
• Build first prototype using multiproject submission
(40 chips)
– Multiple front end designs
– Use full sparsification and I/O
– Add numerous test points
– Chip size = 3.8 mm x 6.5 mm (or full size at
higher cost to understand IR drops)
• Fabricate Engineering Run with optimized front end
and final digital design (12 wafers)
Gerd J. Kunde
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Ray Yarema, FNAL, June 9th
Production Needs
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• 11/8 ships per double tower
• 24 wedges with 2 double towers each
• 1006716 channels north and 1006716 channels
south
• 2 Million channels total
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4000 chips total  need 6000 tested good chips
Gerd J. Kunde
Ray Yarema, FNAL, June 9th
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Production Needs (cont.)
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Useable wafer area = 31,416 x .85 = 26,700 mm2
Chip size = 3.8 x 13 = 49.4 mm2
26,700/49.4 = 540 chips per wafer
Assume 75% yield
Get 405 good chips per wafers
• Need 6000/405 = 15 wafers
• Typical engineering run delivers 10-12 wafers
Gerd J. Kunde
Ray Yarema, FNAL, June 9th
PHX Schedule
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Design specifications completed 10/03
Start design 12/03
Submit prototype 7/04
Prototype testing completed 12/04
Redesign completed for engineering run 1/05
Engineering run back 3/05
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Ray Yarema, FNAL, June 9th
PHX Cost
• Chip design/testing – 2 man-years - $275K (includes
all overhead costs)
• Prototype chip fabrication- $40K (small chip)
• Test board $5K
• Engineering run (10-12 wafers) $200K
~ 15 wafers
total
• 5 Extra wafers using same masks - $25K
• Production wafer level testing –engineering, tech
time, circuit board, probe card - $60K
• Contingency tbd
Gerd J. Kunde
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Endcap Summary
• Readout and bus via
PHX from Fermilab
• Bump bonded
assemblies
• Wedge design
• Umbrella endcap
• Integreation by
LANL/Hytec
Gerd J. Kunde
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