Transcript Document 7604940

Interrupts of 8051
 Introduction
 8051
Interrupt organization
 Processing Interrupts
 Program Design Using Interrupts
 Timer Interrupts
 Serial Port Interrupts
 External Interrupts
 Interrupt Timings
1
Interrupts

An interrupt is the occurrence of a
condition--an event -- that cause a
temporary suspension of a program while
the event is serviced by another program
(Interrupt Service Routine ISR or Interrupt
Handler).
 Interrupt-Driven System-- gives the illusion
of doing many things simultaneously, quick
response to events, suitable for real-time
control application.
 Base level--interrupted program, foreground.
 Interrupt level--ISR, background.
2
Time
Main program (base level, foreground)
Program execution without interrupts
Interrupt
level execution
Base-level
execution
Main
ISR
ISR
ISR
Main
Main
Main
Interrupt (occurs asynchronously)
Return from interrupt instruction
3
8051 Interrupt Organization
5
interrupt sources: 2 external, 2
timer, a serial port
 2 programmable interrupt priority
levels
 fixed interrupt polling sequence
 can be enabled or disabled
 IE (A8H), IP (B8H) for controlling
interrupts
4
Enabling and Disabling Interrupts
IE (Interrupt Enable Register A8H)
Bit
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0



Symbol Bit Address
EA
AFH
AEH
ET2
ADH
ES
ACH
ET1
ABH
EX1
AAH
ET0
A9H
EX0
A8H
Description (1=enable, 0=disable)
Global enable/disable
Undefined
Enable timer 2 interrupt (8052)
Enable serial port interrupt
Enable timer 1 interrupt
Enable external 1 interrupt
Enable timer 0 interrupt
Enable external 0 interrupt
Two bits must be set to enable any interrupt: the individual
enable bit and global enable bit
SETB
ET1
SETB
EA
MOV
IE,#10001000B
5
Interrupt Priority (IP, B8H)
Bit
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0



Symbol Bit Address
PT2
BDH
PS
BCH
PT1
BBH
PX1
BAH
PT0
B9H
PX0
B8H
Description (1=high, 0=low priority)
Undefined
Undefined
Priority for timer 2 interrupt (8052)
Priority for serial port interrupt
Priority for timer 1 interrupt
Priority for external 1 interrupt
Priority for timer 0 interrupt
Priority for external 0 interrupt
0= lower priority, 1= higher priority, reset IP=00H
Lower priority ISR can be interrupted by a high
priority interrupt.
A high priority ISR can not be interrupted.
6
Interrupt Flag Bits
Interrupt
Flag
SFR Register & Bit Position
-----------------------------------------------------------------------------External 0
IE0
TCON.1
External 1
IE1
TCON.3
Timer 1
TF1
TCON.7
Timer 0
TF0
TCON.5
Serial port
TI
SCON.1
Serial Port
RI
SCON.0
Timer 2
TF2
T2CON.7 (8052)
Timer 2
EXF2
T2CON.6 (8052)


The state of all interrupt sources is available through the
respective flag bits in the SFRs.
If any interrupt is disabled, an interrupt does not occur,
but software can still test the interrupt flag.
7
Polling Sequence
 If
two interrupts of the same priority
occur simultaneously, a fixed polling
sequence determines which is
serviced first.
 The polling sequence is External 0 >
Timer 0 > External 1 > Timer 1 >
Serial Port > Timer 2
8
IE register
INT0
1
IT0
Low
priority
interrupt
TF0
INT1
High priority
interrupt
IE0
0
1
IP register
IT1
IE1
0
Interrupt
polling
sequence
TF1
RI
TI
TF2
EXF2
Interrupt
enables
Global Enable
Accent
interrupt
9
Processing Interrupts

When an interrupt occurs and is accepted by the
CPU, the main program is interrupted. The
following actions occur:







The current instruction completes execution.
The PC is saved on the stack.
The current interrupt status is saved internally.
Interrupts are blocked at the level of the interrupt.
The PC is loaded with the vector address of the ISR
The ISR executes.
The ISR finishes with an RETI instruction, which
retrieves the old value of PC from the stack and
restores the old interrupt status. Execution of the
main program continues where it left off.
10
Interrupt Vectors


Interrupt vector = the address of the start of the
ISR.
When vectoring to an interrupt, the flag causing
the interrupt is automatically cleared by hardware.
The exception is RI/TI and TF2/EXF2 which
should be determined and cleared by software.
Interrupt
System Reset
External 0
Timer 0
External 1
Timer 1
Serial Port
Timer 2
Flag
RST
IE0
TF0
IE1
TF1
RI or TI
TF2 or EXF2
Vector Address
0000H (LJMP 0030H)
0003H
000BH
0013H
001BH
0023H
002BH
11
Program Design Using Interrupts
 I/O
event handling:
 Polling:
main program keeps checking
the flag, waiting for the occurrence of
the event. Inefficient in some cases.
 Interrupt-driven: CPU can handle other
things without wasting time waiting for
the event. Efficient, prompt if ISR is not
so complex. Suitable for control
application.
 I/O processor: dedicated processor to
handle most of the I/O job without CPU
intervention. Best but most expensive.
12
8051 Program Design Using
Interrupt
Main:
ORG
LJMP
ORG
.
.
ORG
.
.
ORG
.
.
.
0000H
Main
0003H
000BH
;reset entry point
;takes up 3 bytes
;/INT0 ISR entry point
;8 bytes for IE0 ISR or
; jump out to larger IE0 ISR
;Timer 0 ISR entry point
0030H
;main program entry point
13
Small Interrupt Service
Routine

8 bytes for each interrupt vector. Small
ISR utilizes the space.
 For example: (assume only T0ISR is
needed in the case)
T0ISR:
MAIN:
ORG
LJMP
ORG
.
.
RETI
.
0000H
MAIN
000BH
;only T0ISR
14
Large Interrupt Service
Routine

8 bytes not enough. Use LJMP to large ISR
MAIN:
T0ISR:
ORG
LJMP
ORG
LJMP
ORG
.
.
.
.
RETI
0000H
MAIN
000BH
T0ISR
0030H
; T0 ISR entry point
;above int vectors
; Timer 0 ISR
;return to main
15
A 10-KHz Square Wave on
P1.0 Using Timer Interrupts
T0ISR:
Main:
ORG
LJMP
ORG
CPL
RETI
ORG
MOV
MOV
SETB
MOV
SJMP
0
Main
000BH
P1.0
0030H
TMOD,#02H
TH0,#-50
TR0
IE,#82H
$
;reset entry point
;T0 interrupt vector
;toggle port bit
;T0 MODE 2
;50 mS DELAY
;START TIMER 0
;ENABLE T0 INT
;DO NOTHING
16
Two 7-KHz & 500-Hz Square
Waves Using Interrupts
Main:
ORG
LJMP
ORG
LJMP
ORG
LJMP
ORG
MOV
MOV
SETB
SETB
MOV
SJMP
0
Main
000BH
T0ISR
001BH
T1ISR
0030H
TMOD,#12H
TH0,#-71
TR0
TF1
IE,#8AH
$
;reset entry point
;T0 interrupt vector
;T1 vector
;main starts here
;T0 mode 2, T1 mode 1
;7-kHz using T0
;START TIMER 0
;force T1 int
;ENABLE T0,T1 INT
;DO NOTHING
17
Two 7-KHz & 500-Hz Square
Waves Using Interrupts (cont.)
T0ISR:
T1ISR:
CPL
RETI
CLR
MOV
MOV
P1.7
;7-kHz on P1.7
TR1
;stop T1
TH1,#HIGH(-1000)
TL1,#LOW(-1000)
;1 ms for T1
SETB TR1
;START TIMER 1
CPL P1.6
;500-Hz on P1.6
RETI
18
Serial Port Interrupts

SPISR must check RI or TI and clears it.
 TI occurs at the end of the 8th bit time in
mode 0 or at the beginning of stop bit in
the other modes. Must be cleared by
software.
 RI occurs at the end of the 8th bit time in
mode 0 or half way through the stop bit in
other modes when SM2 =0. If SM2 = 1, RI =
RB8 in mode 2,3 and RI = 1 only if valid
stop bit is received in mode 1.
19
Output ACSII Code Set Using
Interrupt (1)
;dump ASCII codes to serial port
ORG 0
LJMP Main
ORG 0023H
LJMP SPISR
ORG 0030H
Main:
MOV TMOD,#20H
MOV TH1,#-26
SETB TR1
MOV SCON,#42H
MOV A,#20H
MOV IE,#90H
SJMP $
;serial port vector
;main entry point
;Timer 1 mode 2
;use 1200 baud
;start T1
;mode1, set TI to force first
;interrupt; send 1st char.
;send ASCII space first
;enable SP interrupt
;do nothing
20
Output ACSII Code Set Using
Interrupt (2)
SPISR:
Skip:
CJNE
MOV
MOV
INC
CLR
RETI
A,#7FH,Skip ;if ASCII code = 7FH
A,#20H
;wrap back to 20H
SBUF,A;start to transmit
A
TI
;clear TI flag
The CPU speed is much higher than 1200 baud serial transmission.
Therefore, SJMP executes a very large percentage of the time.
Time for one char = (1/1200 baud)(8+1+1) = 8333.3 mS compared to
1 mS machine cycle!
We could replace SJMP instruction with other useful instructions
doing other things.
21
#include
“io51.h”
char
*ptr;
void
InitialUART(int BaudRate)
/*Max baudrate = 9600*/
{
SCON = 0x52;
TMOD = 0x21;
TH1 = 256-(28800/BaudRate);
/*11.059M/384=28800*/
TR1 = 1;
}
static const char msg1[]=“UART interrupt message!!”;
void
main(void)
{
InitialUART(9600);
EA = 1;
ptr = msg1;
ES = 1;
while(1);
/*wait for SP interrupt*/
}
22
interrupt [0x23] void SCON_int(void)
/*Serial port ISR*/
{
if(RI==1)RI=0; /* we did nothing in this program for RxD */
if(TI==1)
{
TI=0;
if(*ptr!=‘\0’)
/*string ends with ‘\0’ character*/
{
SBUF=*ptr;
++ptr;
}
else
{
ES=0; /*complete a string tx, clear ES and let*/
TI=1; /*main program decide next move
*/
}
}
}
23
External Interrupts





/INT0 (P3.2 or pin12) and /INT1 (P3.3 or pin 13)
produce external interrupt in flag IE0 and IE1 (in
TCON) in S5P2.
/INT0 and /INT1 are sampled once each machine
cycle (S5P2) and polled in the next machine cycle.
An input should be held for at least 12 clock
cycles to ensure proper sampling.
Low-level trigger (IT0 or IT1 =0): interrupt when
/INT0 or /INT1 = 0
Negative edge trigger (IT0 or IT1 = 1): interrupt if
sense high on /INT0 or /INT1 in one machine cycle
and low in next machine cycle.
IE0 and IE1 are automatically cleared when CPU
is vectored to the ISR.
24
External Interrupts

If the external interrupt is low-level
triggered (IT0 or IT1 =0), the external
source must hold the request active until
the requested interrupt is actually
generated.
 Then it must deactivate the request before
the ISR is completed, or another interrupt
will be generated.
 Usually, an action taken in the ISR causes
the requesting source to return the
interrupting signal to the inactive state.
25
Furnace Controller
HOT = 0 if T > 21C
INT0
8051
P1.7
COLD = 0 if T < 19C
INT1
1 = solenoid engaged (furnace on) if T < 19C
0 = solenoid disengaged (furnace off) if T > 21C
T = 21C
T = 20C
T = 19C
HOT
COLD
P1.7
26
Furnace Controller
EX0ISR:
EX1ISR:
Main:
Skip:
ORG
LJMP
CLR
RETI
ORG
SETB
RETI
ORG
MOV
SETB
SETB
SETB
JB
CLR
SJMP
0
Main
P1.7
;turn furnace off
13H
P1.7
;turn furnace on
0030H
IE,#85H
IT0
IT1
P1.7
P3.2,Skip
P1.7
$
;enable ext int
;negative edge trigger
;turn furnace on first
;if T>21?
;yes, turn furnace off
;do nothing
27
Intrusion Warning System
8051
INT0
74LS04
P1.7
Door opens
1 sec
P1.7
P1.7
400Hz
1.25 ms
2.5 ms
28
Intrusion Warning System
Main:
Skip:
ORG
LJMP
LJMP
ORG
LJMP
ORG
LJMP
SETB
MOV
MOV
SJMP
0
Main
EX0ISR
0BH
T0ISR
1BH
T1ISR
IT0
TMOD,#11H
IE,#81H
$
;use T0 and R7=20 time 1 s
;use T1 to sound alarm
;negative edge trigger
;16-bit timer
;enable EX0 only
;relax & wait for intrusion
29
Intrusion Warning System
EX0ISR:
T0ISR:
SKIP:
EXIT:
MOV
SETB
SETB
SETB
SETB
RETI
CLR
DJNZ
CLR
CLR
LJMP
MOV
MOV
SETB
RETI
R7,#20
TF0
TF1
ET0
ET1
;20x50000 ms = 1 s
;force T0 ISR
;force T1 ISR
;enable T0 int
;enable T1 int
TR0
;stop T0
R7,SKIP
;if not 20th time, exit
ET0
;if 20th, disable itself
ET1
;and tone
EXIT
TH0,#HIGH(-50000)
;reload 0.05 s
TL0,#LOW(-50000)
;delay
TR0
;turn on T0 again
30
Intrusion Warning System
;
T1ISR:
CLR
MOV
MOV
CPL
SETB
RETI
TR1
TH1,#HIGH(-1250)
TL1,#LOW(-1250)
P1.7
TR1
;stop T1
;count for 400 Hz
;tone
;music maestro
;
31
Interrupt Timing 1
Since
the external interrupt pins are sampled once
each machine cycle, an input high or low should
hold for at least 12 oscillator periods to ensure
sampling.
If the external interrupt is transition-activated, the
external source has to hold the request pin high
for at least one cycle, and then hold it low for at
least one cycle. This is done to ensure that the
transition is seen so that interrupt request flag IEx
will be set.
IEx will be automatically cleared by the CPU when
the service routine is called.
32
Interrupt Timing 2

If the external interrupt is level-activated,
the external source has to hold the
request active until the requested interrupt
is actually generated. Then it has to
deactivate the request before the interrupt
service routine is completed, or else
another interrupt will be generated.
33
Interrupt Timing 3


Response Time
The /INT0 and /INT1 levels are inverted and
latched into IE0 and IE1 at S5P2 of every machine
cycle. The values are not actually polled by the
circuitry until the next machine cycle.
If a request is active and conditions are right for it
to be acknowledged, a hardware subroutine call
to the requested service routine will be the next
instruction to be executed. The call itself takes
two cycles. Thus, a minimum of three complete
machine cycles elapse between activation of an
external interrupt request and the beginning of
execution of the first instruction of the service
routine.
34
Interrupt Timing 4

A longer response time would result if the
request is blocked by one of the 3 previously
listed conditions.
1. An interrupt of equal or higher priority level is
already in progress.
2. The current (polling) cycle is not the final
cycle in the execution of the instruction in
progress. (ensure completion)
3. The instruction in progress is RETI or any
write to the IE or IP registers. (one more
instruction will be executed)
 If an interrupt of equal or higher priority level is
already in progress, the additional wait time
obviously depends on the nature of the other
interrupt’s service routine.
35
Interrupt Timing 5


If the instruction in progress is not in its final
cycle, the additional wait time cannot be more
than 3 cycles, since the longest instructions (MUL
and DIV) are only 4 cycles long, and if the
instruction in progress is RETI or an access to IE
or IP, the additional wait time cannot be more
than 5 cycles (a maximum of one more cycle to
complete the instruction in progress, plus 4
cycles to complete the next instruction if the
instruction is MUL or DIV).
Thus, in a single-interrupt system, the response
time is always more than 3 cycles and less than 9
cycles.
36
Interrupt Response Timing
Diagram: Fastest
37
Interrupt Response Timing
Diagram: Longest
Level 0 ISR
RETI
Main program
MUL AB
Level 0 ISR
Save PC
ISR
9 cycles
Level 1 interrupt occurs
here (missed last chance
before RETI instruction)
38
Interrupt Timing 6
Single-Step Operation
 The 80C51 interrupt structure allows single-step
execution with very little software overhead. As
previously noted, an interrupt request will not be
responded to while an interrupt of equal priority
level is still in progress, nor will it be responded
to after RETI until at least one other instruction
has been executed. Thus, once an interrupt
routine has been entered, it cannot be re-entered
until at least one instruction of the interrupted
program is executed.
 One way to use this feature for single-step
operation is to program one of the external
interrupts (e.g., /INT0) to be level-activated.
39
Interrupt Timing 7


The service routine for the interrupt will terminate
with the following code:
JNB P3.2,$
;Wait Till /INT0 Goes High
JB P3.2,$
;Wait Till /INT0 Goes Low
RETI
;Go Back and Execute One Instruction
Now if the /INT0 pin, which is also the P3.2 pin, is
held normally low, the CPU will go right into the
External Interrupt 0 routine and stay there until
/INT0 is pulsed (from low to high to low). Then it
will execute RETI, go back to the task program,
execute one instruction, and immediately re-enter
the External Interrupt 0 routine to await the next
pulsing of P3.2. One step of the task program is
executed each time P3.2 is pulsed.
40
Interrupt Timing 8
Reset
 The reset input is the RST pin, which is the input
to a Schmitt Trigger.
 A reset is accomplished by holding the RST pin
high for at least two machine cycles (24 oscillator
periods), while the oscillator is running. The CPU
responds by generating an internal reset.
 The external reset signal is asynchronous to the
internal clock. The RST pin is sampled during
State 5 Phase 2 of every machine cycle. The port
pins will maintain their current activities for 19
oscillator periods after a logic 1 has been
sampled at the RST pin; that is, for 19 to 31
oscillator periods after the external reset signal
has been applied to the RST pin.
41
Reset Timing
42
Interrupt Timing 9

The internal reset algorithm writes 0s to all
the SFRs except the port latches, the
Stack Pointer, and SBUF.
 The port latches are initialized to FFH
(input mode), the Stack Pointer to 07H,
and SBUF is indeterminate.
 The internal RAM is not affected by reset.
On power up the RAM content is
indeterminate.
43