Transcript Camera Electronics Box SOLAR DYNAMICS OBSERVATORY Dr N R Waltham CEB Lead Engineer

SOLAR DYNAMICS OBSERVATORY
Camera Electronics Box
Dr N R Waltham
CEB Lead Engineer
[email protected]
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 1
Contents
Overview
Parts / Circuits
– Team and Responsibilities
– Parts Procurement Levels
– Top-Level Requirements
– CEB Parts
– CCD Architectural Design
– CCD Readout Modes
– CCD Electronics Design
Requirements
– CEB Architectural Design
 Waveform Generator ASIC
 CCD Clock Drivers
 CDS/ADC Video Processing
ASIC
– Card-Level Architectural Design
 CCD Bias / DAC ASIC
– Overview of Box Design
 SMCSLite SpaceWire ASIC
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 2
Contents
DC-DC Power Converter
– Requirements
– Options
– Grounding
Resource Requirements
Camera EGSE
– Requirements
– Hardware
– Camera Control Software
– Image Display / Analysis
Software
– Size
– Mass Budget
– Power Budget
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 3
CEB - Team
RAL (Space Science and Technology Department)
–
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Nick Waltham
Jim Lang
Sarah Dunkin
James King
Andy Marshall
Mathew Clapp
Bill Duell
Dave Parker
Dave Smart
Jayne Fereday
Dave Kelsh
Duncan Drummond
John Rainnie
Mattias Wallner
Camera system design and CCD electronics
RAL Programme Management
Project Management
Analogue electronics / PCB design / Parts.
Waveform Generator ASIC / FPGA / digital design.
Analogue / digital electronics development / test.
Camera electronics (Prototyping / Development / test)
Reliability Analysis
Enclosure (box) design
Thermal Analysis
PA / QA
Camera EGSE Real-Time software
Camera EGSE image display / analysis software
Camera EGSE test cryostat / electro-optics test / calibration
RAL (Instrumentation Department Microelectronics Group)
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–
–
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Andrea Fant
Lawrence Jones
Bill Gannon
Marcus French
HMI Preliminary Design Review – Nov. 18 &19, 2003
Analogue ASIC design / management.
CDS/ADC ASIC specialist.
Digital ASIC design support.
ASIC Group Management
Camera Electronics Box (CEB)
Waltham
Page 4
CEB Requirements
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Each CEB to drive one SDO 4k x 4k pixel CCD through any or all of its quadrant
readout ports.
CCD driver circuitry optimised for the new SDO E2V 4k x 4k pixel CCD.
CCD readout at up to 2 Mpixel/s through any or all of the quadrant readout ports.
14 bit analogue-to-digital conversion with programmable video gain and video offset.
Video digitisation sensitivity and dynamic range matched to an anticipated CCD full
well capacity of 150-200k electrons, and a CCD readout noise of  25 electrons rms.
Programmable CCD readout waveform patterns, sequences, and readout modes.
Windowed readout of at least two windows, and pixel summing options.
Software control of critical CCD bias voltages (TBC).
Interface to the HEB via the SpaceWire Adaptation of IEEE1355.
Camera Enclosure to be as small and light-weight as possible.
EEE Components to be GSFC 311-INST-001.
Components to be radiation tolerant to > 35 Krads total dose (inside box with 5mm
walls).
Components to be latch-up free; otherwise protected with latch-up current trips.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 5
CEB Requirements
14.
Operationally, the camera will provide at least the following modes:
CLEAR


Fast CLEAR through CCD Dump-Drain
Flexible CLEAR routine by appropriate programming of the CEB’s waveform
generator.
EXPOSURE


CCD’s image area clocks held at appropriate voltage levels.
Serial register clocks can be individually programmed to be high, low, or
clocking.
READOUT





Flexible READOUT routines by appropriate programming of the CEB’s
waveform generator.
Readout through all four ports, two ports, or one port.
Windowed readout of at least two windows.
Full-frame, or windowed readout with n x m pixel summing.
Continuous clocking.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 6
CCD Architectural Design and Readout Modes
3- + SW Serial_Left
3- + SW Serial_Right
DG_top
Readout Modes
OS4
Up
Down
OS3
R
R
Up and Down
DOS4
Left
DOS3
Right
4- Imaging + TG_top
Left and Right
4- Imaging + TG_bottom
Bias Voltages
OD
= Output Drain
RD
= Reset Drain
SS
= Substrate
DD
= Dump Drain
OG1
= Output Gate 1
OG2
= Output Gate 2
OG1
OG2 CCD Gain Adjust
OS1
OS2
R
DOS1
R
3- + SW Serial_Left
DOS2
3- + SW Serial_Right
DG_bottom
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 7
Electronics Design Requirements - Thin-Oxide CCD
CCD Clocks
No. of Drivers
8 Channels
2 Channels
1 Channel
5 Channels
1 Channel
1 Channel
Voltage
7-8 V
7-8 V
7-8 V
5V
5V
10 V
Function
4 Phase Imaging Area (top and bottom)
Transfer Gate (top and bottom)
Dump Gate (top and bottom)
3 Phase Serial register (left and right)
Summing Well (left and right)
Reset Clock
23 V
14 V
0-9 V
24 V
2V
3V
Output Transistor Drain
Reset Transistor Drain
Substrate Voltage
Dump Drain
Output Gate 1
Output Gate 2
Bias Voltages
OD
RD
SS
DD
OG1
OG2
1
1
1
1
1
1
Channel
Channel
Channel
Channel
Channel
Channel
Notes
1. Separate OD, RD (and JD) drivers for each output to minimise crosstalk.
2. Software Control of bias voltages incorporated within baseline design.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 8
CEB Architectural Design
Power
ACTEL
Glue
Logic
I2C
VIDEO
DATA
LVDS
5MHz
UART1
5MHz
I2C
4
CDS/ADC
ASICs
ACTEL
Glue
Logic
LVDS
CDS/ADC
Control
LVDS for high
speed data/clocks
down backplane
SpaceWire Interface
SpaceWire
Interface
9S Micro-D
LVDS
Tx/Rx
32K
FIFO
LVDS
VIDEO
DATA
SpaceWire
Camera Host
Interface
(SMCSLite)
Video
4 x CDS/ADC Video
Processor ASICs
CCD Flex
CCD
21S Micro-D
Power
I2C
8 Channel
DAC ASIC
I2C
DC Bias
CCD DC Bias
Voltage
Generators
25P Micro-D
Housekeeping
ADC
Power
40MHz
XTAL
I2C
I2C
Clocks
5MHz
Waveform
Generator
ASIC
ACTEL
Glue
Logic
CCD Flex
CCD Clock
Shapers and
Drivers
Clocks
CCD Flex
31P Micro-D
LVDS
Filters
Screened sub-enclosure
+5V
+15V
+30V
0V
Output
Filter
DC-DC
Converter(s)
Input
Filter
In-rush
Current
Limiter
28V Primary
S/C Power
ASIC Timing
Generator
9P D-Sub
Backplane
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 9
Architectural Design - CCD Video Card
Backplane
5V
2.5V
Regulator
Mode and Gating Control
RT54SXS ACTEL FPGA
5V
Current
Trip
3.3V
Regulator
CDS/ADC
ASIC
Video Data
14
14
Video Data Mux
5V
Current
Trip
8
LVDS
TX
CDS/ADC
ASIC
Video
Data
Mux Control
Clocks
3
14
14
8
LVDS
RX
5V
Current
Trip
Reset
Current
Trip
CDS/ADC
ASIC
Video Data
14
I2C
I2C
I2C
DOS1
VID+ I/P
OS2
VID- I/P
DOS2
VID+ I/P
OS3
VID- I/P
DOS3
VID+ I/P
OS4
VID- I/P
DOS4
3.3V
Regulator
14
I2C
CDS/ADC
ASIC
14
14
5V
VID- I/P
21S
Micro-D
3.3V
Regulator
Video Data
Mux
Control
Clocks
OS1
3.3V
Regulator
Video Data
Video Data
VID+ I/P
3
3
CDS/ADC
Control
Clocks
CDS/ADC control clocks
5
5
LVDS
RX
+5V
LVDS Data transmission down backplane at 16 MHz
HMI Preliminary Design Review – Nov. 18 &19, 2003
CDS/ADC ASIC
Camera Electronics Box (CEB)
Waltham
Page 10
Architectural Design - CCD Driver Card
Backplane
5V
Current
Trip
80MHz
Xtal
80MHz
3.3V
Regulator
40MHz
WGA CCD
Waveform
Generator
ASIC
15V
IO, TG, DG
CLK
5V
HO
I2C
TG, DG
31P
Micro-D
11
TABLE-ACTIVE
I2C
ISL74422
x11
IO,
IO, TG, DG
CONFIG
Table-Active
9V
Regulator
5V
Decoupling
HO
I2C
ACS245
x2
HO
ACS245
x1
SW
UC1708
x1
OR
5
3
CDS/ADC control clocks
5
LVDS
TX
SW
Mux Control Clocks
2
5V
CDS/ADC
clocks
LVDS
TX
Reset
SW
2
Mux
Control
clocks
Reset
5V
Decoupling
15V
OR
10V
Regulator
OR
5MHz Clk
1
+5V
+15V
LVDS
TX
5V
5MHz
2.5V
Regulator
Mode and Gating Control
RT54SXS ACTEL FPGA
Image Area, Serial Register and
Reset Clock Drivers
Waveform Generator ASIC
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 11
Architectural Design - CCD Bias Card
Low Noise CCD Bias Drivers
Backplane
5V
5V
2.5V
Regulator
Current
Trip
JD1. JD2,
JD3, JD4
1
Mode and Gating Control
54SXS ACTEL FPGA
I2C
25P
Micro-D
HS-OP470RH
x4
3.3V
Regulator
RAL 8 CHANNEL
DAC ASIC
7
HS-OP470RH
x4
OD1, OD2,
OD3, OD4
HS-OP470RH
X4
RD1, RD2,
DD1, DD2
HS-OP470RH
x3
SS, OG1,
OG2
1
I2C
I2C
3
Software Bias
Control
5V
Mux
Current
Trip
Reset
2
Telemetry
ADC
3
ADC Trigger
7
Housekeeping
Telemetry Data
+5V
+15V
Bridge Amplifier
CCD PRT
8
+30V
+5V
Housekeeping Telemetry
Address Select
PCB Temperature
Sensor
+15V
+30V
4
H/K Telemetry Mux
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 12
Architectural Design - SpaceWire Card
Backplane
LVDS Backplane signals
SMCSLite
SpaceWire ASIC
5MHz CLK
1
LVDS
RX
5MHz CLK
Mode and Gating Control
RT54SXS ACTEL FPGA
Video Data
8
FIFO Load
Clocks
2
LVDS
RX
LVDS
RX
200
Mbits/s
Link
200
Mbits/s
Link
8
16K
FIFO
8
8
16K
FIFO
8
2
9S
Micro-D
4
FIFO
I/P
Port
200 Mbits/s
Link Rate
I2C
3
Reset
5V
+5V
LVDS
TX/RX
8
Reset
I2C
SMCSLite
SpaceWire ASIC
2.5V
Regulator
UART-to-I2C
converter
UART1
16k word 16 bit wide FIFO Buffer
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 13
Architectural Design - Power Converter
EMC
Feedthroughs
9P D-Sub
Output
Filtering
+30V
+30V
+15V
+15V
+15V (UF)
+5V
+5V
+5V (UF)
0V
0V
+30V (UF)
M3GT280515T
DC-DC
Converter
+28V
+28V_RTN
EMC
Filter
In-Rush
Current-Limiter
and
Current-Trip
+28V
+28V_RTN
0V (UF)
In-Rush Current Limiter
and Current Trip
Input Filter
Output Filter
HMI Preliminary Design Review – Nov. 18 &19, 2003
M3GT280515T or ART2815T
DC-DC Converter
Camera Electronics Box (CEB)
Waltham
Page 14
Overview of Box Design
Backplane
Filtered Feed-throughs
mounted on removable
shelf
DC-DC Converter
(ARF2815T shown)
Flexi-Rigid PCB connection
to Filtered Feed-throughs
Output Filter PCB
Input Filter PCB and
Power Connector
HMI Preliminary Design Review – Nov. 18 &19, 2003
EMI Filter (ARF2815T option only)
Camera Electronics Box (CEB)
Waltham
Page 15
Overview of Box Design
PCBs added
PCBs screwed
down to side rails
Dog House Cover added
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 16
Overview of Box Design
Top Cover added
Front Panel added
Representative Feet shown - TBD for HMI and AIA
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 17
Parts / Circuits
 Overview of EEE Parts Specification
 Waveform Generator ASIC
 CCD Clock Drivers
 CDS/ADC Video Processing ASIC
 DAC ASIC
 SMCSLite SpaceWire ASIC
 DC-DC Converter
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 18
EEE Part Specification
Parts Procurement Levels:
– ICs
MIL-PRF-38535 QML-Level V (preferred), QML-Level Q,
or up-screened MIL-STD-883-B + PIND + Life-Test (minimum)
– RAL ASICs:
0.35m radiation-tolerant CMOS (from AMS).
Packaging to Mil Std 883E 5004 Class B plus PIND.
– Actives:
Transistors/Diodes: JANTXV (minimum), JANS (Interface parts).
– Passives:
Resistors:
Capacitors:
MIL-R-55342, or equivalent,
MIL-C-55681/55365, or equivalent,
– Connectors:
Micro-D:
Standard-D:
Backplane:
MIL-PRF-83513, or equivalent,
MIL-PRF-24308 , or equivalent,
MIL-PRF-55302
Radiation Issues:
– 100 krad, latch-up free parts where possible, and > 35 krad parts in all other cases.
– Latch-up protection for parts / sub-systems below minimum SEL threshold.
 All parts except ASICs procured by LMSAL through EEE Parts Control Board.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 19
RAL Waveform generator ASIC
Single chip to generate all the timing signals needed to read out a CCD
Space Projects:
 SMEI (Birmingham/UCSD/AFRL)
 ROSETTA MODULUS (Open University)
 DCIXS (ESA SMART-1)
 TOPSAT (Mosaic-1)
 STEREO/SECCHI (NRL/Birmingham)
 Earthshine (Mosaic-2)
Other Projects:
Fabrication on Rad-Hard
TEMIC DMILL process.
 Lab evaluation / lab work
SDO
 Second-Generation:- WGS2003
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 20
RAL WGS2003 ASIC – Features
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Up to 32-bit wide logic Waveform pattern generation.
≥ 80MHz output pattern rate.
Waveform Output Inversion Register – to program polarity of each Waveform output.
8-bit wide Waveform “dwell” function for each Waveform state.
Up to 32 configurable Waveform patterns.
Seamless Waveform pattern generation under the control of Table sequences.
Up to 32 configurable Table sequences.
Parameter specified (up to 65535) or endless looping of Wave sequences.
Nested looping of Wave sequences, with a nested-loop depth of up to four.
Halt, externally triggered re-start, Table synchronization output and jump instruction for
exotic control sequences.
Programming via a 3 wire serial I2C interface running at up to 1Mbit/sec.
Auto incrementing memory programming function to speed up RAM programming.
RAM Double bit error detection and single bit error correction using hamming code.
Status register to show Waveform/Table activity, Detected errors, etc.
RAM self-test function to check every memory location for errors.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 21
RAL WGS2003 ASIC – Block Diagram
Jump
Register
Status Register
SDA_Out
SDA_In
I2C Interface
and Auto
Incrementors
SCLK
Address
32
Inversion
Mask
16
Status
32
6
Reset
Clock
Start/Stop
RAM
96
locations
TABLE
RAM
1024
locations
E
D
A
C
10
Error Logic
E
D
A
C
WAVE RAM
1024
locations
D
W
E
L
L
E
D
A
C
Mem_Tst_Atv
2
5
24
6
32
Error Logic
8
Error Logic
Mem_Status
7
Dwell
generator
RAM Address Multiplexers
RAM Test
Table
Processor
Wave Processor
Trig
Sync
Jump
HMI Preliminary Design Review – Nov. 18 &19, 2003
Tbl_Atv
Camera Electronics Box (CEB)
Waltham
Page 22
RAL WGS2003 ASIC – Implementation
Design
–
Synchronous Design in VHDL.
–
Prototyping target – ACTEL Axcelerator FPGA
Flight target (Baseline)
–
ACTEL RTAX2000S
–
–
–
–
–
Straight forward translation from Axcelerator to RTAX2000S.
Projected ≥ 200 krads total dose and Single-Event-Latch-up (SEL) immunity.
Eliminates ASIC packaging / testing / up-screening risks.
Physically large package.
Availability ?
or
–
AMS 0.35µm ASIC on AMS (austriamicrosystems) 0.35µm C35 OPTO CMOS
–
–
–
Smaller dedicated package.
FPGA-to-ASIC translation / packaging / testing / up-screening / schedule issues.
AMS 0.35µm C35 OPTO (20 µm epitaxial CMOS) process SEL threshold ?
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 23
RAL WGS2003 ASIC – ACTEL RTAX2000S
RTAX2000S on SDO PCB Layout
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 24
CCD Clock Drivers – Requirements and Solutions
 5 V Serial Register Clock Drivers
Intersil ACTS245 QML-V 300 krads SELth > 100MeV
 3-phase clocks at 2 MHz.
 ~ 750 pF loading per phase (~ 5x SECCHI CCD).
 9-10 V Reset Clock Driver.
Unitrode UC1708 QML-V bipolar part, Radiation ?
 50ns-100ns pulse at 2 MHz repetition rate.
 ~ few pF loading.
 7-8 V Imaging Area Clock Drivers
Intersil ISL74422ARH QML-V 300 krads SEL immune
 4-phase clocks at ~ 10 KHz
 ~ 100 nF loading per phase .
 7-8 V Transfer / Dump Gate Clock Drivers Intersil ISL74422ARH
 10 KHz / 1 Hz clocks.
 ~ 2500 pF loading.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 25
Serial Register Clock Drivers
Clocking SECCHI CCD42-40
+ additional load capacitors
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 26
RAL CDS/ADC ASIC
Features
DC Restoration of the CCD video signal.
Fully differential-input preamplifier and CDS.
1 V video signal input range.
Fully differential pipelined 16 bit ADC with digital error
correction.
Operation at up to at least 1 Mpixels/s readout rate.
10 bit Programmable Offset (+/- 500 mV).
7 bit Programmable Gain (gain = x 1 to x 3).
Input referred system noise  3.2 adu rms.
3-wire serial interface to program video gain and offset.
Triple-voting internal control Logic to protect against
single-event upsets (SEUs).
Single 3.3 V power supply.
Supply current ~ 125 mA.
0.35 m CMOS process.
84-pin CQFP with 0.025 inch lead pitch.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 27
CDS/ADC Video Processing
RAL SECCHI CDS/ADC ASIC
 1 Mpixels/s CCD preamplifier, CDS processor and ADC.
 Input noise = 0.75 ADU rms [ 1V input range].
 125mA @ 3.3V @ 1 Mpixels/s [ 625mW from 5V] [ x4 for SDO].
 Radiation tolerant, but bulk AMS 0.35m CSI CMOS process (Latch-up sensitive).
New Features for SDO
 Operation up to 2 Mpixels/s readout rate.
 AMS 0.35 m C35 OPTO (20 µm epitaxial) process
 Better SEL threshold?
Optimal 50 ns
Reference Level
Sampling Period
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Optimal 50 ns Signal
Level Sampling
Period
Waltham
Page 28
CCD Bias / DAC ASIC
Requirements
 8 channels software programmable CCD bias voltages.
 Compact solution.
 Typical SECCHI CEB DC Bias Circuits
Original Concept was to replace this with
a programmable DAC voltage source
Vr ef
SO T
+3 0V
4
Bia s S et
3
2
10 0n
1
Vb ias
-
11
Bia s S et
+
U7 A
HS 9-O P47 0AR H
10 K0
10 K0
HMI Preliminary Design Review – Nov. 18 &19, 2003
10 0n
Camera Electronics Box (CEB)
Waltham
Page 29
CCD Bias / DAC ASIC
Vr ef
+30V
4
Bias Set
3
Bias Set
Digital
Control
Input
100n
1
Vbias
-
11
2
+
U8A
HS9-OP470ARH
10K0
10K0
100n
But what is really needed is a
programmable variable resistor.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 30
CCD Bias / DAC ASIC
6 bit control over a 4 V range
Vr ef
 63mV / LSB precision
Bias Set
 More than sufficient!
RAL ASIC
or
ACTEL FPGA ?
R
D0
HMI Preliminary Design Review – Nov. 18 &19, 2003
D1
Bias Set
2R
D2
4R
D3
8R
D4
Camera Electronics Box (CEB)
100n
16R
32R
D5
Waltham
Page 31
SMCSLite SpaceWire ASIC
http://www.estec.esa.nl/microelectronics/presentation/#SMCSLite
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 32
SMCSLite SpaceWire ASIC
Operation







200 Mbits/s Link speed.
16 bit FIFO input mode - ok provided you send an even number of bytes.
Up to 8 byte header.

But responsibility of computer to program the 8 bytes before CCD readout.
CCD frame transmitted as a single 32 Mbyte packet.

SMCSLite can sustain 16 Mbytes/s data rate.
End of image indicated by End-Of-Packet flag (EOP1).
Errors indicated with EOP2.
End-Of-Line flag included within pixel data (15th bit).
New version of SMCSLite due 2004 Q2 (Baseline)
 Better FIFO handling.
 Pin compatible with original.
 New process:- ATMEL 0.5µm Rad Hard MG2RTP – 300 krads / Latch-up immune.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 33
DC-DC Power Converter
Requirements
 +28V Primary Input with in-rush current limiting.
 +5V, 3.3V, and 2.5V for logic (3.3V and 2.5V rails to be derived from +5V).
 +3.3V for ASICs (3.3V rail to be derived from +5V).
 +5V for CCD Serial Register Clock Driver supplies.
+15V for CCD Image Area / Dump Gate Clock Driver supplies.
 +30V for CCD biasing.
 Secondary side filtering of all power.
 Good regulation, low noise, sufficient power, and maximum conversion efficiency.
 Radiation hard or radiation tolerant design.
Design / Configuration
 Triple rail (+5V, +/-15V) module configured as +5V, +15V, +30V.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 34
DC-DC Power Converter
M3GT280515T
 M3GT280515T is Baseline for SDO CEB.
 Depends on minimum secondary rail currents.
 Consider ART2815T as used in SECCHI CEB as backup.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 35
DC-DC Power Converter
Power Conversion and Filtering Design
–
–
–
–
Hybrid modular DC-DC converter - M3GT280515T (Baseline) or ART2815T
EMI filter to provide common mode and differential filtering.
In-rush current limiting / current trip circuit before EMI filter.
Common mode and differential filtering on secondary rails at outputs of
DC-DC converter
Grounding
– Primary power isolated within CEB
– Secondary power returns connected to chassis throughout box.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 36
CEB Resource Requirements
• Volume:
150 mm x 131 mm x 95 mm
(excluding mounting feet and connector extrusions).
• Mass:
2.95 kgs (no contingency added).
• Power:
11.4 W (exposure), 15.0 W (readout) with JFETs
10.7 W (exposure), 14.3 W (readout) without JFETs
(no contingency added).
• TC/TM Hardware Standard:
SpaceWire Adaptation of IEEE1355 With LVDS Signals.
• TC/TM Data Rate:
200Mbits/s.
• Power Connector:
9-Way Standard-D Connector (Plug).
• TC/TM Connector:
9-Way MDM Micro-D Connector (Socket).
• CCD Connector(s):
21S, 25P, 31P MDM Micro-D Connectors.
• Synchronisation:
None needed.
• Temperatures:
-10°C to +40°C Operating Temperature Range.
-20°C to +50°C Survival Temperature Range.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 37
Mass Budget
SUB-SYSTEM SUB-TOTALS
Item
CCD Video Card
CCD Driver Card
CCD Bias Card
SpaceWire Card
Backplane
Power Converter
Enclosure
Total Mass (gms)
Contingency (%)
Unit Mass (g)
187
192
187
150
180
358
1673
Quantity
1
1
1
1
1
1
1
2926
0
0
TOTAL MASS with contingency (gms)
HMI Preliminary Design Review – Nov. 18 &19, 2003
Subtotal
187
192
187
150
180
358
1673
2926
Camera Electronics Box (CEB)
Waltham
Page 38
Power Budget
Summary
Item
CCD Video Card
CCD Driver Card
CCD Bias Card
Camera SpaceWire Interface Card
Pexposure (mW)
3350.0
1582.5
3360.2
730.0
Preadout (mW)
3500.0
3060.0
3360.2
1950.0
Secondary power sub-systems sub-totals
9022.7
11870.2
Average DC-DC Power Converter Efficiency (%)
Power Converter (loss)
79.0
2398.4
79.0
3155.4
TOTALS with 0% contingency (Watts)
11.4
15.0
Includes JFET buffers
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 39
Camera EGSE Requirements
Enhanced STEREO/SECCHI system for 4-port 4k x 4k SDO CCD readout.
IDL Image Display running on LINUX-based PC.
 Camera programming and set-up (Waveforms, Readout tables, Video gain / offset).
 Camera Control: i.e., CLEAR, Exposure, Readout commands.
 Image display and adjustment of grey levels.
 Zoom window with adjustable zoom factor.
 Saving of images to disc in FITS format, and recalling images from disc.
 Basic low-level image processing functions (i.e., addition, subtraction, and division of
any 2 images).
 Feature extraction.
 Basic statistical analysis of the extracted image data including mean pixel value, max
pixel value, min pixel value, variance and RMS values.
 Profile plotting through image data.
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 40
CEB EGSE Hardware - Options
SpaceWire Interfaces to PCs
–
4Links PCI Card (as used in STEREO / SECCHI)
–
–
–
–
–
–
Based on SMCS332 (big brother of SMCSLite).
3 Links with theoretical 200 Mbits/s rate.
Linux and Win2k Drivers (SECCHI uses LINUX).
Only works if CCD Line transfer time is ≥ 250 µs
i.e. Effective throughput ≤ 16 Mbytes/s.
4Links PCI Card
University of Dundee 8Links / USB2 Box
–
–
–
–
FPGA Design.
8 Links.
Throughput achieves 16 Mbytes/s (with the right PC!)
Need PC with DMA (SCSI) discs.
Baseline for SDO
Dundee 8Links / USB2 Box
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 41
Camera Control Software
Camera Control Panel
•
Camera Setup Window
– Waveform/Table Load
File Source
– Set Video Gain/Offset
– Reset Buttons
– Clear CCD Command
– Exposure Command
– Read CCD Command
• Camera Setup Window
– Table Number Assignment to
Clear/Readout Commands
– Data Dump-File Details
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 42
Image Display / Analysis Software
Main Image Viewer Pane
Preview (Default) /
Adaptive Mode Pane
Loaded Files
Image Preview
of Selected File
Cursor Position and Value
HMI Preliminary Design Review – Nov. 18 &19, 2003
Camera Electronics Box (CEB)
Waltham
Page 43