Transcript An Impact Parameter Trigger for DØ Bill Lee Florida State University CHEP03
An Impact Parameter Trigger for D Ø
Bill Lee Florida State University CHEP03 San Diego, Ca.
Introduction + Motivation Design Status
Contributing Institutions
Boston University
U. Heintz, M. Narain, E. Popkov (PD), L. Sonnenschein (PD), J. Wittlin (PD), K. Black (GS), S. Fatakia (GS), A. Zabi (GS), A. Das (GS), W. Earle (Eng), E. Hazen (Eng), S. Wu (Eng) Columbia University
H. Evans, G. Steinbr ück (PD), T. Bose (GS), A. Qi (Eng) Florida State University
H. Wahl, H. Prosper, S. Linn, T. Adams, B. Lee (PD), S. Tentindo Repond (PD), S. Sengupta (GS), J. Lazoflores (GS), D. Kau (GS) SUNY Stony Brook
J. Hobbs, W. Taylor (PD), H. Dong (GS), C. Pancake (Eng), B. Smart (Eng), J. Wu (Eng)
Bill Lee 25 March 2003 2
The D Ø Run 2 Detector
SMT Bill Lee
New state of the art tracker and trigger
25 March 2003 3
Silicon Microstrip Tracker
4 H-Disks 12 F-Disks 6 Barrels
6 10-cm long barrels + 16 disks 793,000 channels of electronics SMT hit resolution ~10
m
25 March 2003 Bill Lee 4
The Central Fiber Tracker
Scintillating Fibers Up to |
| =1.7
20 cm < r < 51 cm 8 double layers CFT: 77,000 channels
CFT 25 March 2003 Bill Lee 5
Level 1 Central Track Trigger
-
Custom hardware + firmware Preprogrammed track equations matched to hit patterns Sensitive to beam offsets beyond ~1mm Installation complete, mostly commissioned
25 March 2003 Bill Lee 6
The D Ø Trigger System
2.3 MHz p Crossing frequency 2.3MHz
p But data acquisition rate is limited to 50 Hz
3 Level Trigger System
L1 Decision time 4.2
s
5 k
Hz
L2 Decision time 100 s
1 k
Hz
L3 Decision time ~50ms
50 Hz
•
Hardware based
•
Simple Signatures in each Sub-Detector
•
Software and Firmware based
•
Physics Objects e,
,jets, tracks
•
Software based
•
Simple versions of reconstruction algorithms
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The Idea
B Decay Products Flight Length
mm’s
Collision Decay Vertex Impact Parameter Tracks
b quarks are key in many areas:
Higgs Physics (ZH
- -
)
top physics ( t->Wb)
B physics
b quarks have a finite lifetime
travel mm’s before they decay
displaced tracks
Would like to trigger on displaced tracks
using the precision of the Silicon Tracker
Impact parameter resolution 35
m (includes 30
m from beamspot) Need to make very fast decisions!
25 March 2003 Bill Lee 8
Physics Motivation for STT
-
Increase inclusive bb production yield six-fold with low enough threshold to see Z
-
bb signal
-
Control sample for b-jet energy calibration, bb mass resolution, b trigger and tagging efficiencies Top quark physics
Factor of 2 improvement in top mass systematics due to improved jet
energy scale calibration
-
Double trigger efficiency for ZH
(
-
)(bb) by rejecting QCD gluons and light-quark jets b-quark physics
Lower p T threshold on single lepton and dilepton triggers (B O
, B s mixing, etc.) Increase B d o
J/
Y
K S yield by 50% (CP violation)
STT proposed 1998 as addendum to D Ø baseline
Received approval and funding in 1999
Bill Lee 25 March 2003 9
Conceptual Design
Bill Lee road data Fiber Road Card SMT data Silicon Trigger Card Card Silicon Card Card Card Track Fit Card
L1CTT
tracks in CFT
Define road in SMT Select SMT hits in roads Fit trajectory to L1CTT+SMT hits. Measure
pT,
impact parameter, azimuth Send results to L2 Pass L1CTT information to L2 Send SMT clusters to L3
L2CTT 25 March 2003 10
6 Identical Crates with 1 Fiber Road Card 9 Silicon Trigger Cards 2 Track Fit Cards CPU
STT Design
L2 Global
to L2CTT SBC
SCL in
TFC STC STC STC STC STC FRC STC STC STC STC TFC
L2 Global
to L2CTT Bill Lee 1 2 3 4 5 6 7 8 9 10 Sector 1 11 12 13 14 Layout of Run 2A STT Crate 15 16 17 18 19 20 21 Sector 2 25 March 2003 11
Motherboard and Communication Links
9Ux400 mm VME64x compatible 3 33-MHz PCI busses for on board communications Data communicated between cards via point-to-point links (LVDS) (Link Transmitter and Receiver Cards) Control signals sent over backplane using dedicated lines VME bus used for Level 3 readout and initialization/monitoring PCI-PCI bridges Universe II
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Fiber Road Card (FRC) Design
Receives tracks from L1 Central Track Trigger Communicates with trigger framework via SCL receiver card Transmits tracks and trigger info to other cards Manages L3 buffering and readout via Buffer Controller (BC) daughter cards on each motherboard
Implemented in 6 Altera FPGA’s
FLEX 10k30E and 10k50E
30/50 k gates
24/40 k bits of RAM
208/240 pins
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Link Transmitter Board
Fiber Road Card (FRC) Design
FRC Link Receiver Board Buffer controller 25 March 2003 Bill Lee 14
Silicon Trigger Card (STC) Design
Performs Silicon clustering and cluster-road matching
Clusters Neighbouring SMT hits (axial and stereo) Each STC processes 8 silicon inputs simultaneously Axial clusters are matched to ±1mm-wide roads around each fiber track via precomputed LUT Mask bad strips and apply pedestal/gain corrections (via LUTs)
Implemented in FPGAs
Main functionality implemented in XILINX VIRTEX XCV812E
~ 800k gates
This project made possible with state
1.1 Mbits of RAM
of-the-art FPGAs
560 pin BGA package
Bill Lee
3 PCI interfaces use Altera ACEX EP1K30 chips
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Road LUT
Silicon Trigger Card (STC) Design
FPGA Bill Lee 25 March 2003 16
Track Fit Card (TFC) Design
Performs final SMT cluster filtering and track fitting
Receives 2 CFT hits and axial SMT clusters in CFT road Lookup table used to convert hardware to physical coordinates
Selects clusters closest to road center and performs linearized track fit using precomputed matrix elements stored in on-board LUT
(
r
)
r
0
Require hits in only 3 out of 4 silicon layers Output to L2CTT via Hotlink cards
C code running on 8 DSPs:
Bill Lee
TI TMS320C6203B fixed point DSP
300 Mhz
two independent 32-bit I/O busses
performs 16 bit multiply/32 bit add instructions
rated at 2400 MIPS
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Coordinate Conversion LUT Hotlink Card
Track Fit Card (TFC) Design
Matrix LUT Bill Lee DSP 25 March 2003 18
STT Performance
= 20 m
50 GeV muons No beam spot
Monte Carlo
Plots from STT Trigger Simulator
Exact DSP fitting code used
Has been instrumental in developing the fitting algorithm
Produces test vectors for all cards
Bill Lee 25 March 2003 19
System Integration
All hardware at hand Used fake data sender (tracks to FRC and hits to STC) to verify inputs, transfers between boards and for rate tests Presently able to run at global run rates for ~10000 events
Integration with the D0 trigger system ongoing Will soon integrate with L1 central track trigger, STC reading real data
Currently Instrumenting a 30 ° sector/ half crate
Full track reconstruction
Output to L3 and private DAQ for L2
Full Commissioning ongoing
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Bill Lee
Run2b: Silicon Detector Upgrade
Single sided silicon, barrels only Inner (vertexing) layers L0, L1
Axial only
mounted on carbon support
Outer (tracking) layers L2-L5
Axial and stereo Stave structures
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Run 2B Silicon Track Trigger
Run 2B STT can process hit information from 5 of the 6 Run 2B SMT layers Achieved by adding 1 STC and 2 TFC’s per crate
Bill Lee 25 March 2003 22
Conclusions
The Silicon Track Trigger is crucial for a large part of the Run 2 physics program
Higgs, top, B physics Proposed in 1998 as addendum to D0 baseline Received funding in 1999
Project far advanced All hardware for Run 2a at hand!
Installing of full system Full commissioning beginning in the next month
Run 2b upgrades involve additional hardware
25 March 2003 Bill Lee 23