Transcript CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers

CS/EE 3700 : Fundamentals of
Digital System Design
Chris J. Myers
Lecture 7: Flip-flops, Registers, Counters
Chapter 7
Sequential Circuits
• Combinational – output depends only on
the input.
• Sequential – output depends on input and
past behavior.
– Require use of storage elements.
– Contents of storage elements is called state.
– Circuit goes through sequence of states as a
result of changes in inputs.
Sensor
Set
Memory
element
On Off
Reset
Figure 7.1
Control of an alarm system
Alarm
A
Figure 7.2
B
A simple memory element
Load
A
Data
B
TG1
TG2
Figure 7.3
A controlled memory element
Output
Reset
Set
Figure 7.4
Q
A memory element with NOR gates
R
Qa
Qb
S
(a) Circuit
t1
t2
S
R
Qa Qb
0
0
0/11/0
0
1
0
1
1
0
1
0
1
1
0
0
(no change)
(b) Truth table
t3
t4
t5
t6
t7
t8
t9
t 10
1
R
0
1
S
0
1
Qa
?
0
1
Qb
?
0
Time
(c) Timing diagram
Figure 7.5
A latch built with NOR gates
R
R
Q
Clk
Q
Clk
S
R
Q(t + 1)
0
x
x
Q(t) (no change)
1
0
0
Q(t) (no change)
1
0
1
0
1
1
0
1
1
1
1
x
S
S
(a) Circuit
(b) Truth table
1
Clk
0
1
R
0
S
1
Q
Clk
S
0
R
1
?
Q
0
Q
(d) Graphical symbol
1
?
0
Time
(c) Timing diagram
Figure 7.6
Gated SR latch
Q
S
Q
Clk
Q
R
Figure 7.7
Gated SR latch with NAND gates
S
D
(Data)
Q
Clk
Q
R
(a) Circuit
Clk D
0
1
1
x
0
1
Q(t + 1)
D
Q(t )
0
1
Clk Q
(b) Truth table
Figure 7.8
Gated D latch
Q
(c) Graphical symbol
D
(Data)
S
Q
Clk
Q
R
(a) Circuit
t1
t2
t3
t4
Clk
D
Q
Time
(d) Timing diagram
Figure 7.8
Gated D latch
t su
th
Clk
D
Q
Figure 7.9
Setup and hold times
Master
D
Clock
D
Q
Slave
Qm
Clk Q
D
Q
Clk Q
Qs
Q
Q
(a) Circuit
Clock
D
D
Q
Qm
Q
Q = Qs
(b) Timing diagram
Figure 7.10
Master-slave D flip-flop
(c) Graphical symbol
1
P3
P1
2
5
Q
6
Q
Clock
P2
3
D
D
4
P4
(a) Circuit
Figure 7.11
Clock
Q
Q
(b) Graphical symbol
A positive-edge-triggered D flip-flop
D
Clock
Q
Qa
Clk Q
Qa
D
D
Q
Qb Clock
Q
Qb
D
Qa
D
(a) Circuit
Figure 7.12
Q
Qc
Qb
Q
Qc
Qc
(b) Timing diagram
Comparison of level-sensitive and edge-triggered
Preset
D
Q
Clock
Q
Clear
(a) Circuit
Preset
D
Q
Q
Clear
(b) Graphical symbol
Figure 7.13
Master-slave D flip-flop with Clear and Preset
Preset
Q
Clock
Q
Preset
D
D
Q
Q
Clear
Clear
(a) Circuit
(b) Graphical symbol
Figure 7.14 Positive-edge-triggered D flip-flop with Clear and Preset
Clear
D
D
Clock
Figure 7.15
Q
Q
Q
Q
Synchronous reset for a D flip-flop
D
Q
T
Q(t + 1)
0
Q(t )
1
Q(t )
Q
(b) Truth table
T
Q
Q
T
Q
Clock
Q
(a) Circuit
(c) Graphical symbol
Clock
T
Q
(d) Timing diagram
Figure 7.16 T flip-flop
J
D
K
Q
Q
Q
Q
Clock
(a) Circuit
J K Q ( t + 1)
0
0
1
1
0
1
0
1
Q (t)
0
1
Q (t )
(b) Truth table
Figure 7.17
J
Q
K
Q
(c) Graphical symbol
JK flip-flop
Summary of Terminology
• Basic latch – cross-coupled NAND/NOR
• Gated latch – output changes when clk = 1.
– Gated SR latch
– Gated D latch
• Flip-flop – output changes only on clk edge.
– Edge-triggered flip-flop
– Master-slave flip-flop
In
Clock
D
Q
Q1
D
Q
Q
Q2
D
Q
Q
Q3
Q
(a) Circuit
In
Q1
Q2
Q3
Q4 = Out
t0
1
0
0
0
0
t1
0
1
0
0
0
t2
1
0
1
0
0
t3
1
1
0
1
0
t4
1
1
1
0
1
t5
0
1
1
1
0
t6
0
0
1
1
1
t7
0
0
0
1
1
(b) A sample sequence
Figure 7.18
A simple shift register
D
Q
Q
Q4
Out
Parallel output
Q3
D
Q
Q2
D
Q
Serial
input
Q
Q
Shift/Load
Q1
D
Q
Q
Parallel input
Figure 7.19
A simple shift register
Q0
D
Q
Q
Clock
1
T
Clock
Q
T
Q
Q
T
Q
Q0
Q
Q
Q1
Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count
0
1
2
3
4
5
6
(b) Timing diagram
Figure 7.20
A three-bit up-counter
7
0
1
T
Clock
Q
T
Q
Q
T
Q
Q0
Q
Q
Q1
Q2
(a) Circuit
Clock
Q0
Q1
Q2
Count
0
7
6
5
4
3
2
(b) Timing diagram
Figure 7.21
A three-bit down-counter
1
0
Clock cycle
0
1
2
3
4
5
6
7
8
Q2 Q1 Q0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
Table 7.1
0
1
0
1
0
1
0
1
0
Q1 changes
Q2 changes
Derivation of the synchronous up-counter
1
T
Q
T
Q
Q0
Clock
Q
T
Q1
Q
T
Q
Q2
Q
Q3
Q
Q
(a) Circuit
Clock
Q0
Q1
Q2
Q3
Count 0
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15
(b) Timing diagram
Figure 7.22
A four-bit synchronous up-counter
0
1
Enable
Clock
T
Q
Q
T
Q
Q
T
Q
Q
Clear
Figure 7.23
Inclusion of enable and clear capability
T
Q
Q
Enable
D Q
Q0
Q
D Q
Q1
Q
D Q
Q2
Q
D Q
Q3
Q
Clock
Figure 7.24 A four-bit counter with D flip-flops
Output
carry
Enable
D0
D1
0
1
D Q
Q0
Q
0
1
D Q
Q1
Q
D2
0
1
D Q
Q2
Q
D3
0
1
D Q
Q3
Q
Output
carry
Load
Clock
Figure 7.25 A counter with parallel-load capability
1
Enable
0
D0
Q0
0
D1
Q1
0
D2
Q2
Load
Clock
Clock
(a) Circuit
Clock
Q0
Q1
Q2
Count 0
1
2
3
4
5
0
(b) Timing diagram
Figure 7.26
A modulo-6 counter with synchronous reset
1
1
T
Clock
Q
Q0
Q
T
Q
Q
T
Q1
Q
Q2
Q
(a) Circuit
Clock
Q0
Q1
Q2
Count 0
1
2
3
4
5
0
1
(b) Timing diagram
Figure 7.27
A modulo-6 counter with asynchronous reset
2
1
0
0
0
0
Enable
D0
D1
D2
D3
Q0
Q1
Q2
Q3
BCD 0
Q0
Q1
Q2
Q3
BCD 1
Load
Clock
Clock
Clear
0
0
0
0
Enable
D0
D1
D2
D3
Load
Clock
Figure 7.28
A two-digit BCD counter
Q0
Q1
Qn ”
Start
D
Q
D
Q
Q
D
Q
Q
Clock
(a) An n -bit ring counter
Q0 Q1 Q2 Q3
y0
y1
y2
y3
2-to-4 decoder
w1
w0
En
1
Clock
Clock
Q1
Q0
Two-bit up-counter
Start
Figure 7.29 Ring counter
Clear
(b) A four-bit ring counter
Q
1
Q0
D
Q
Q
Q1
D
Q
Q
Reset
Clock
Figure 7.30
Johnson counter
Qn – 1
D
Q
Q
Figure 7.31
Three types of storage elements in a schematic
Data
Clock
Latch
Figure 7.32
Gated D latch generated by CAD tools
Clock
Interconnection wires
PAL-like block
D
0
Data
1
Latch
1
Flip-–op
Q
0
0
D
Q
1
0
D
Q
1
0
T
Q
(Other macrocells not shown)
Figure 7.33 Implementation of a circuit in a CPLD
1
Toggle
Figure 7.34
Timing simulation of storage elements
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY altera ;
USE altera.maxplus2.all ;
ENTITY flipflop IS
PORT ( D, Clock
Resetn, Presetn
Q
END flipflop ;
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Structure OF flipflop IS
BEGIN
dff_instance: dff PORT MAP ( D, Clock, Resetn, Presetn, Q ) ;
END Structure ;
Figure 7.35
Instantiating a D flip-flop from a package
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY implied IS
PORT ( A, B
AeqB
END implied ;
: IN
: OUT
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF implied IS
BEGIN
PROCESS ( A, B )
BEGIN
IF A = B THEN
AeqB <= '1' ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.36
Implied memory
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT ( D, Clk
Q
END latch ;
: IN
: OUT
STD_LOGIC ;
STD_LOGIC) ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PROCESS ( D, Clk )
BEGIN
IF Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.37
Code for a gated D latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN
STD_LOGIC ;
Q
: OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.38
Code for a D flip-flop
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY flipflop IS
PORT ( D, Clock : IN
Q
: OUT
END flipflop ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
Q <= D ;
END PROCESS ;
END Behavior ;
Figure 7.39
Code for a D flip-flop using WAIT UNTIL
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock
Q
END flipflop ;
: IN
: OUT
STD_LOGIC ;
STD_LOGIC) ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.40
D flip-flop with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock
Q
END flipflop ;
: IN
: OUT
STD_LOGIC ;
STD_LOGIC) ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Resetn = '0' THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.41
D flip-flop with synchronous reset
Figure 7.42
The lpm_ff parameterized flip-flop module
Figure 7.43
An adder with registered feedback
Figure 7.44
Timing simulation
Timing Constraints
•
•
•
•
•
2 ns from register clocked to data output.
8 ns for adder to produce sum.
4 ns for sum to propagate to register input.
3 ns for setup time.
Clock cycle time must be 17 ns.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY lpm ;
USE lpm.lpm_components.all ;
ENTITY shift IS
PORT ( Clock
Reset
Shiftin, Load
R
Q
END shift ;
: IN
: IN
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
ARCHITECTURE Structure OF shift IS
BEGIN
instance: lpm_shiftreg
GENERIC MAP (LPM_WIDTH => 4, LPM_DIRECTION => "RIGHT")
PORT MAP (data => R, clock => Clock, aclr => Reset,
load => Load, shiftin => Shiftin, q => Q ) ;
END Structure ;
Figure 7.45
Instantiation of the lpm_shiftreg module
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY reg8 IS
PORT ( D
Resetn, Clock
Q
END reg8 ;
: IN
STD_LOGIC_VECTOR(7 DOWNTO 0) ;
: IN
STD_LOGIC ;
: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF reg8 IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= "00000000" ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.46
Code for an eight-bit register with asynchronous clear
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regn IS
GENERIC ( N : INTEGER := 16 ) ;
PORT ( D
: IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn, Clock : IN
STD_LOGIC ;
Q
: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.47
Code for an n-bit register with asynchronous clear
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY muxdff IS
PORT ( D0, D1, Sel, Clock : IN
Q
: OUT
END muxdff ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF muxdff IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Sel = '0' THEN
Q <= D0 ;
ELSE
Q <= D1 ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.48
Code for a D flip-flop with a 2-to-1 multiplexer on the D input
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shift4 IS
PORT ( R
L, w, Clock
Q
END shift4 ;
: IN
: IN
: BUFFER
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
ARCHITECTURE Structure OF shift4 IS
COMPONENT muxdff
PORT ( D0, D1, Sel, Clock : IN
STD_LOGIC ;
Q
: OUT STD_LOGIC ) ;
END COMPONENT ;
BEGIN
Stage3: muxdff PORT MAP ( w, R(3), L, Clock, Q(3) ) ;
Stage2: muxdff PORT MAP ( Q(3), R(2), L, Clock, Q(2) ) ;
Stage1: muxdff PORT MAP ( Q(2), R(1), L, Clock, Q(1) ) ;
Stage0: muxdff PORT MAP ( Q(1), R(0), L, Clock, Q(0) ) ;
END Structure ;
Figure 7.49
Hierarchical code for a four-bit shift register
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shift4 IS
PORT ( R
: IN
Clock
: IN
L, w
: IN
Q
: BUFFER
END shift4 ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF shift4 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF L = '1' THEN
Q <= R ;
ELSE
Q(0) <= Q(1) ;
Q(1) <= Q(2);
Q(2) <= Q(3) ;
Q(3) <= w ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.50
Alternative code for a shift register
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shift4 IS
PORT ( R
: IN
Clock
: IN
L, w
: IN
Q
: BUFFER
END shift4 ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF shift4 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF L = '1' THEN
Q <= R ;
ELSE
Q(3) <= w ;
Q(2) <= Q(3) ;
Q(1) <= Q(2);
Q(0) <= Q(1) ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.51
Code that reverses the ordering of statements
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shiftn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R
: IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Clock
: IN
STD_LOGIC ;
L, w
: IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftn ;
ARCHITECTURE Behavior OF shiftn IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF L = '1' THEN
Q <= R ;
ELSE
Genbits: FOR i IN 0 TO N-2 LOOP
Q(i) <= Q(i+1) ;
END LOOP ;
Q(N-1) <= w ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.52
Code for an n-bit left-to-right shift register
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Clock, Resetn, E
Q
END upcount ;
: IN
STD_LOGIC ;
: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
ARCHITECTURE Behavior OF upcount IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = '0' THEN
Count <= "0000" ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
IF E = '1' THEN
Count <= Count + 1 ;
ELSE
Count <= Count ;
END IF ;
END IF ;
END PROCESS ;
Q <= Count ;
END Behavior ;
Figure 7.53
Code for a four-bit up-counter
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY upcount IS
PORT ( R
Clock, Resetn, L
Q
END upcount ;
: IN
: IN
: BUFFER
INTEGER RANGE 0 TO 15 ;
STD_LOGIC ;
INTEGER RANGE 0 TO 15 ) ;
ARCHITECTURE Behavior OF upcount IS
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = '0' THEN
Q <= 0 ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
IF L = '1' THEN
Q <= R ;
ELSE
Q <= Q + 1 ;
END IF;
END IF;
END PROCESS;
END Behavior;
Figure 7.54
A four-bit counter with parallel load, using INTEGER signals
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY downcnt IS
GENERIC ( modulus : INTEGER := 8 ) ;
PORT ( Clock, L, E : IN
STD_LOGIC ;
Q
: OUT INTEGER RANGE 0 TO modulus-1 ) ;
END downcnt ;
ARCHITECTURE Behavior OF downcnt IS
SIGNAL Count : INTEGER RANGE 0 TO modulus-1 ;
BEGIN
PROCESS
BEGIN
WAIT UNTIL (Clock'EVENT AND Clock = '1') ;
IF E = '1' THEN
IF L = '1' THEN
Count <= modulus-1 ;
ELSE
Count <= Count-1 ;
END IF ;
END IF ;
END PROCESS;
Q <= Count ;
END Behavior ;
Figure 7.55
Code for a down-counter
Data
Extern
Bus
Clock
R1
R1in
R1out
R2
R2in
R2out
Rk
Rkin
Control circuit
Function
Figure 7.56
A digital system with k registers
Rkout
Bus
R1out
D
R2out
Q
D
Q
Q
D
Q
R1i n
Q
D
Q
Q
R2i n
Clock
R1
Figure 7.57 Details for connecting registers to a bus
Q
R2
Register Swapping
• Consider 3 register example (R1, R2, R3)
that swaps contents of R1 and R2 using R3.
• Three steps:
– Contents of R2 transferred to R3.
– Contents of R1 transferred to R2.
– Contents of R3 transferred to R1.
R2out ,R3in
w
Clock
D
Q
Q
R1out ,R2in
D
Q
R3out ,R1in
D
Q
Reset
Figure 7.58
A shift-register control circuit
Q
Q
R2out ,R3in
R1out ,R2in
R3out ,R1in
Reset
w
D PQ
Q
Clock
Figure 7.59
D
Q
Q
A modified control circuit
D
Q
Q
R2out ,R3in
R1out ,R2in
R3out ,R1in
w
D
Q
Q
Clock
D
Q
Q
D
Q
Q
Reset
Figure 7.60
A control circuit that does not require flip-flop preset inputs
Bus
R1in
R2in
R1
R2
Rkin
Clock
Data
S0
Multiplexers
Sj – 1
Figure 7.61
Using multiplexers to implement a bus
Rk
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R
: IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock
: IN
STD_LOGIC ;
Q
: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Rin = '1' THEN
Q <= R ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.62
Code for an n-bit register with enable
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY trin IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( X : IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
E : IN
STD_LOGIC ;
F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END trin ;
ARCHITECTURE Behavior OF trin IS
BEGIN
F <= (OTHERS => 'Z') WHEN E = '0' ELSE X ;
END Behavior ;
Figure 7.63
Code for an n-bit tri-state buffer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shiftr IS -- left-to-right shift register with async reset
GENERIC ( K : INTEGER := 4 ) ;
PORT ( Resetn, Clock, w
: IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;
END shiftr ;
ARCHITECTURE Behavior OF shiftr IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Genbits: FOR i IN K DOWNTO 2 LOOP
Q(i) <= Q(i-1) ;
END LOOP ;
Q(1) <= w ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.64
Code for the shift-register controller
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE components IS
COMPONENT regn -- register
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R
: IN
Rin, Clock
: IN
Q
: OUT
END COMPONENT ;
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
COMPONENT shiftr -- left-to-right shift register with async reset
GENERIC ( K : INTEGER := 4 ) ;
PORT
( Resetn, Clock, w
: IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;
END component ;
COMPONENT trin -- tri-state buffers
GENERIC ( N : INTEGER := 8 ) ;
PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
E : IN STD_LOGIC ;
F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END COMPONENT ;
END components ;
Figure 7.65
Package and component declarations
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.components.all ;
ENTITY swap IS
PORT ( Data
: IN
Resetn, w
: IN
Clock, Extern : IN
RinExt
: IN
BusWires : INOUT
END swap ;
STD_LOGIC_VECTOR(7 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(1 TO 3) ;
STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF swap IS
SIGNAL Rin, Rout, Q : STD_LOGIC_VECTOR(1 TO 3) ;
SIGNAL R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
BEGIN
control: shiftr GENERIC MAP ( K => 3 )
PORT MAP ( Resetn, Clock, w, Q ) ;
Rin(1) <= RinExt(1) OR Q(3) ;
Rin(2) <= RinExt(2) OR Q(2) ;
Rin(3) <= RinExt(3) OR Q(1) ;
Rout(1) <= Q(2) ; Rout(2) <= Q(1) ; Rout(3) <= Q(3) ;
Figure 7.66 A digital system with a bus
tri_ext: trin PORT MAP ( Data, Extern, BusWires ) ;
reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;
tri1: trin PORT MAP ( R1, Rout(1), BusWires ) ;
tri2: trin PORT MAP ( R2, Rout(2), BusWires ) ;
tri3: trin PORT MAP ( R3, Rout(3), BusWires ) ;
END Behavior ;
Figure 7.66 A digital system with a bus
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.components.all ;
ENTITY swapmux IS
PORT ( Data
Resetn, w
Clock
RinExt
BusWires
END swapmux ;
: IN
: IN
: IN
: IN
: BUFFER
STD_LOGIC_VECTOR(7 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(1 TO 3) ;
STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF swapmux IS
SIGNAL Rin, Q : STD_LOGIC_VECTOR(1 TO 3) ;
SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SIGNAL R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
BEGIN
control: shiftr GENERIC MAP ( K => 3 )
PORT MAP ( Resetn, Clock, w, Q ) ;
… con’t
Figure 7.67a
Using multiplexers to implement a bus
Rin(1) <= RinExt(1) OR Q(3) ;
Rin(2) <= RinExt(2) OR Q(2) ;
Rin(3) <= RinExt(3) OR Q(1) ;
reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;
encoder:
WITH Q SELECT
S <= "00" WHEN "000",
"10" WHEN "100",
"01" WHEN "010",
"11" WHEN OTHERS ;
muxes: --eight 4-to-1 multiplexers
WITH S SELECT
BusWires <= Data WHEN "00",
R1 WHEN "01",
R2 WHEN "10",
R3 WHEN OTHERS ;
END Behavior ;
Figure 7.67b
Using multiplexers to implement a bus (con’t)
(ENTITY declaration not shown)
ARCHITECTURE Behavior OF swapmux IS
SIGNAL Rin, Q : STD_LOGIC_VECTOR(1 TO 3) ;
SIGNAL R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
BEGIN
control: shiftr GENERIC MAP ( K => 3 )
PORT MAP ( Resetn, Clock, w, Q ) ;
Rin(1) <= RinExt(1) OR Q(3) ;
Rin(2) <= RinExt(2) OR Q(2) ;
Rin(3) <= RinExt(3) OR Q(1) ;
reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;
muxes:
WITH Q SELECT
BusWires <= Data
R2
R1
R3
END Behavior ;
Figure 7.68
WHEN "000",
WHEN "100",
WHEN "010",
WHEN OTHERS ;
Simplified code for describing a bus
Figure 7.69
Timing simulation
Figure 7.70 A digital system that implements a simple processor
Table 7.2
Operations performed in the processor
T0 T1 T2 T3
y0 y1 y2 y3
2-to-4 decoder
w1
w0
En
1
Clock
Clear
Figure 7.71
Q1
Q0
Up-counter
Reset
A part of the control circuit for the processor
I0
I1
X
I2 I3
X1 X2 X3
Y 0 Y1 Y2 Y3
y0 y1 y2 y3
y0 y1 y2 y3
y0 y1 y2 y3
2-to-4 decoder
w1 w0
En
2-to-4 decoder
w1 w0
En
0
1
2-to-4 decoder
w1 w0
En
1
Clock
FRin
Function Register
f1
f 0 Rx1 Rx0 Ry1 Ry0
Function
Figure 7.72
The function registers and decoders
1
Processor Control Logic
Clear = w T0 + Done
FRin = wT0
Extern = I0T1
Done = (I0 + I1)T1 + (I2 + I3)T3
Ain = (I2 + I3)T1
Gin = (I2 + I3)T2
Gout = (I2 + I3)T3
AddSub = I3
R0in = (I0 + I1)T1X0 + (I2 +I3)T3X0
R0out = I1T1Y0 + (I2 + I3)(T1X0 + T2Y0)
Table 7.3
Control signals asserted in each operation/time step
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Clear, Clock : IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;
END upcount ;
ARCHITECTURE Behavior OF upcount IS
BEGIN
upcount: PROCESS ( Clock )
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF Clear = '1' THEN
Q <= "00" ;
ELSE
Q <= Q + '1' ;
END IF ;
END IF;
END PROCESS;
END Behavior ;
Figure 7.73
Code for a two-bit up-counter with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
USE work.subccts.all ;
ENTITY proc IS
PORT ( Data
Reset, w
Clock
F, Rx, Ry
Done
BusWires
END proc ;
: IN
: IN
: IN
: IN
: BUFFER
: INOUT
STD_LOGIC_VECTOR(7 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF proc IS
SIGNAL Rin, Rout : STD_LOGIC_VECTOR(0 TO 3) ;
SIGNAL Clear, High, AddSub : STD_LOGIC ;
SIGNAL Extern, Ain, Gin, Gout, FRin : STD_LOGIC ;
SIGNAL Count, Zero : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SIGNAL T, I, X, Y : STD_LOGIC_VECTOR(0 TO 3) ;
SIGNAL R0, R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL A, Sum, G : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL Func, FuncReg : STD_LOGIC_VECTOR(1 TO 6) ;
… con’t
Figure 7.74a
Code for the processor
BEGIN
Zero <= "00" ; High <= '1' ;
Clear <= Reset OR Done OR (NOT w AND T(0)) ;
counter: upcount PORT MAP (
Clear, Clock, Count ) ;
decT: dec2to4 PORT MAP ( Count, High, T );
Func <= F & Rx & Ry ;
FRin <= w AND T(0) ;
functionreg: regn GENERIC MAP ( N => 6 )
PORT MAP ( Func, FRin, Clock, FuncReg ) ;
decI: dec2to4 PORT MAP ( FuncReg(1 TO 2), High, I ) ;
decX: dec2to4 PORT MAP ( FuncReg(3 TO 4), High, X ) ;
decY: dec2to4 PORT MAP ( FuncReg(5 TO 6), High, Y ) ;
Extern <= I(0) AND T(1) ;
Done <= ((I(0) OR I(1)) AND T(1)) OR ((I(2) OR I(3)) AND T(3)) ;
Ain <= (I(2) OR I(3)) AND T(1) ;
Gin <= (I(2) OR I(3)) AND T(2) ;
Gout <= (I(2) OR I(3)) AND T(3) ;
AddSub <= I(3) ;
… con’t
Figure 7.74b
Code for the processor (con’t)
RegCntl:
FOR k IN 0 TO 3 GENERATE
Rin(k) <= ((I(0) OR I(1)) AND T(1) AND X(k)) OR
((I(2) OR I(3)) AND T(3) AND X(k)) ;
Rout(k) <= (I(1) AND T(1) AND Y(k)) OR
((I(2) OR I(3)) AND ((T(1) AND X(k)) OR (T(2) AND Y(k)))) ;
END GENERATE RegCntl ;
tri_extern: trin PORT MAP ( Data, Extern, BusWires ) ;
reg0: regn PORT MAP ( BusWires, Rin(0), Clock, R0 ) ;
reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;
tri0: trin PORT MAP ( R0, Rout(0), BusWires ) ;
tri1: trin PORT MAP ( R1, Rout(1), BusWires ) ;
tri2: trin PORT MAP ( R2, Rout(2), BusWires ) ;
tri3: trin PORT MAP ( R3, Rout(3), BusWires ) ;
regA: regn PORT MAP ( BusWires, Ain, Clock, A ) ;
alu:
WITH AddSub SELECT
Sum <= A + BusWires WHEN '0',
A - BusWires WHEN OTHERS ;
regG: regn PORT MAP ( Sum, Gin, Clock, G ) ;
triG: trin PORT MAP ( G, Gout, BusWires ) ;
END Behavior ;
Figure 7.74c
Code for the processor (con’t)
… (ENTITY declaration not shown)
ARCHITECTURE Behavior OF proc IS
SIGNAL X, Y, Rin, Rout : STD_LOGIC_VECTOR(0 TO 3) ;
SIGNAL Clear, High, AddSub : STD_LOGIC ;
SIGNAL Extern, Ain, Gin, Gout, FRin : STD_LOGIC ;
SIGNAL Count, Zero, T, I : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SIGNAL R0, R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL A, Sum, G : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL Func, FuncReg, Sel : STD_LOGIC_VECTOR(1 TO 6) ;
BEGIN
Zero <= "00" ; High <= '1' ;
Clear <= Reset OR Done OR (NOT w AND NOT T(1) AND NOT T(0)) ;
counter: upcount PORT MAP (
Clear, Clock, Count ) ;
T <= Count ;
Func <= F & Rx & Ry ;
FRin <= w AND NOT T(1) AND NOT T(0) ;
functionreg: regn GENERIC MAP ( N => 6 )
PORT MAP ( Func, FRin, Clock, FuncReg ) ;
I <= FuncReg(1 TO 2) ;
decX: dec2to4 PORT MAP ( FuncReg(3 TO 4), High, X ) ;
decY: dec2to4 PORT MAP ( FuncReg(5 TO 6), High, Y ) ;
controlsignals: PROCESS ( T, I, X, Y )
BEGIN
… con’t
Figure 7.75a
Alternative code for the processor
Extern <= '0' ; Done <= '0' ; Ain <= '0' ; Gin <= '0' ;
Gout <= '0' ; AddSub <= '0' ; Rin <= "0000" ; Rout <= "0000" ;
CASE T IS
WHEN "00" => -- no signals asserted in time step T0
WHEN "01" => -- define signals asserted in time step T1
CASE I IS
WHEN "00" => -- Load
Extern <= '1' ; Rin <= X ; Done <= '1' ;
WHEN "01" => -- Move
Rout <= Y ; Rin <= X ; Done <= '1' ;
WHEN OTHERS => -- Add, Sub
Rout <= X ; Ain <= '1' ;
END CASE ;
WHEN "10" => -- define signals asserted in time step T2
CASE I IS
WHEN "10" => -- Add
Rout <= Y ; Gin <= '1' ;
WHEN "11" => -- Sub
Rout <= Y ; AddSub <= '1' ; Gin <= '1' ;
WHEN OTHERS => -- Load, Move
END CASE ;
WHEN OTHERS => -- define signals asserted in time step T3
CASE I IS
Figure 7.75b
Alternative code for the processor (con’t)
WHEN "00" => -- Load
WHEN "01" => -- Move
WHEN OTHERS => -- Add, Sub
Gout <= '1' ; Rin <= X ; Done <= '1' ;
END CASE ;
END CASE ;
END PROCESS ;
reg0: regn PORT MAP ( BusWires, Rin(0), Clock, R0 ) ;
reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;
regA: regn PORT MAP ( BusWires, Ain, Clock, A ) ;
alu: WITH AddSub SELECT
Sum <= A + BusWires WHEN '0',
A - BusWires WHEN OTHERS ;
regG: regn PORT MAP ( Sum, Gin, Clock, G ) ;
Sel <= Rout & Gout & Extern ;
WITH Sel SELECT
BusWires <= R0 WHEN "100000",
R1 WHEN "010000",
R2 WHEN "001000",
R3 WHEN "000100",
G
WHEN "000010",
Data WHEN OTHERS ;
END Behavior ;
Figure 7.75c
Alternative code for the processor (con’t)
Figure 7.76
Timing simulation of the processor
VDD
c9
VDD
c1 c0
RL
Clock
10-bit counter
(a) Clock divider
Figure 7.77 A reaction-timer circuit
V LED
(b) LED circuit
VDD
VDD
RL
R
a b
w
0
1
c9
1
D
g a b
Converter
Converter
w0 w1 w2 w3
w0 w1 w2 w3
BCD1
BCD0
Q
Q
E
Two-digit BCD counter
Reset
Clear
(c) Push-button switch, LED, and 7-segment displays
Figure 7.77 A reaction-timer circuit
g
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY BCDcount IS
PORT ( Clock
: IN
STD_LOGIC ;
Clear, E
: IN
STD_LOGIC ;
BCD1, BCD0 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END BCDcount ;
ARCHITECTURE Behavior OF BCDcount IS
BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
IF Clear = '1' THEN
BCD1 <= "0000" ; BCD0 <= "0000" ;
… con’t
Figure 7.78a
Code for a two-digit BCD counter
ELSIF E = '1' THEN
IF BCD0 = "1001" THEN
BCD0 <= "0000" ;
IF BCD1 = "1001" THEN
BCD1 <= "0000";
ELSE
BCD1 <= BCD1 + '1' ;
END IF ;
ELSE
BCD0 <= BCD0 + '1' ;
END IF ;
END IF ;
END IF;
END PROCESS;
END Behavior ;
Figure 7.78b
Code for a two-digit BCD counter (con’t)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY reaction IS
PORT ( c9, Reset
w, Pushn
LEDn
Digit1, Digit0
END reaction ;
: IN
: IN
: OUT
: BUFFER
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(1 TO 7) ) ;
ARCHITECTURE Behavior OF reaction IS
COMPONENT BCDcount
PORT ( Clock
: IN
STD_LOGIC ;
Clear, E
: IN
STD_LOGIC ;
BCD1, BCD0 : BUFFER
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END COMPONENT ;
COMPONENT seg7
PORT ( bcd
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;
END COMPONENT ;
SIGNAL LED : STD_LOGIC ;
SIGNAL BCD1, BCD0 : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
… con’t
Figure 7.79a
Code for the reaction timer
BEGIN
flipflop: PROCESS
BEGIN
WAIT UNTIL c9'EVENT AND c9 = '1' ;
IF Pushn = '0' THEN
LED <= '0' ;
ELSIF w = '1' THEN
LED <= '1' ;
END IF ;
END PROCESS ;
LEDn <= NOT LED ;
counter: BCDcount PORT MAP ( c9, Reset, LED, BCD1, BCD0 ) ;
seg1 : seg7 PORT MAP ( BCD1, Digit1 ) ;
seg0 : seg7 PORT MAP ( BCD0, Digit0 ) ;
END Behavior ;
Figure 7.79b
Code for the reaction timer (con’t)
Figure 7.80
Simulation of the reaction-timer circuit
Summary
•
•
•
•
Latches / flip-flops
Registers / counters
VHDL
Design examples