Transcript Leakage Power Analysis and Comparison of Deep Submicron Logic Gates

A Class Presentation for VLSI Course
by : Fatemeh Refan
Based on the work
Leakage Power Analysis and
Comparison of Deep Submicron
Logic Gates
Geoff Merrett and Bashir M. Al-Hashimi
ESD Group, School of Electronics and Computer Science, University of
Southampton, UK
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and
Simulation;
14th International Workshop, PATMOS 2004, Santorini, Greece
September 15-17, 2004
Outline
 Background
 Introduction
 Design of Low Order Gates
 Design of Higher Order Gates
 Input Pattern Ordering
Background
 Design styles :
 COMP
 Partitioned
 CPL
 TG
 DCVSL
 DPL
 LP
 Power Consumption
 Leakage Current Estimation
Complementary CMOS (COMP)
 NMOS pull-down & dual
PMOS pull-up
 Complementary inputs
 High number of
transistors (XOR : 12)
 …
NAND
XOR
Partitioned Logic (NAND)
 Breaks down a higher order gate into lower order
gates
 Faster than a CMOS high order gate
Complementary Pass Logic (CPL)
 Two NMOS logic
networks
 Two small pull-up
PMOS transistors for
swing restoration
 Two output inverters for
the complementary
outputs
 Number of transistors
(10)
NAND
XOR
Transmission Gate (TG) XOR
 An NMOS to pull-down
and a PMOS to pull-up
 Solution to the voltagedrop problem
 Based on the
Complementary
properties of NMOS and
PMOS
 Low number of
transistors (4)
Differential Cascade Voltage Switch
Logic (DCVSL) XOR
 Two NMOS logic
networks
 Two small pull-up
PMOS transistors for
swing restoration
 Differential logic and
positive feedback
 Number of transistors
(8)
Double Pass Logic (DPL) XOR
 Dual-rail pass-gate logic
 Both NMOS & PMOS
logic networks are used
in parallel
 High number of
transistor (12)
Low Power (LP) XOR
 Using drivers to
complete the high
output logic when input
is “11”
 Low number of
transistors (6)
Power consumption
 Dynamic : switching
 Short-circuit
 Static:
 Gate leakage
 Sub-threshold leakage:
 weak inversion current
Ptotal  Pdyn  Psc  VS I leak
I leak  I S  I ox
Leakage Current Estimation
 Number of stacked
transistors
 Parallel or series
transistors
I S  I 0 exp(
Vgs  VTH
nVT
)(1  e
Vds
VT
)
I S1  I S 2  I S 3  ...  I Sn
Introduction
 Decreasing the Dimensions ?


Effects on power consumption
Solution and limitation
 Leakage power reduction techniques:




Supply voltage reduction
Supply voltage gating
Multiple or increased threshold voltages
Minimizing leakage power consumption in
sleep states
Parameters Variation
 Berkeley Predictive Technology Models (BPTM)
 Basic gates : NAND, NOR, XOR
 Three DSM process tech. : 0.07, 0.1, and 0.13um
 Different design styles :
 NAND, NOR : COMP, Partitioned, CPL
 XOR : COMP, CPL, TG, DCVSL, DPL, LP
 FAN-in : 2, 4, 6, 8
 Input ordering
Design of Low Order Gates
(NAND/NOR)
 The leakage power of a CPL gate is four times that of the COMP gate


There are no stacks
Extra leakage current is drawn through:


level-restoring
output-driving circuitry
 The leakage power in a CMOS circuit increases as the technology
shrinks
Design of Low Order Gates (XOR)
 LP (area, speed and
power):




The least leakage
power
Few transistors
Low delays
Low dynamic power
 COMP
 Low leakage power
 Less than 30%
worse than LP
Design of Higher Order Gates
 COMP gate consumes
less power

more transistors there
in the stack
 Partitioned logic is
faster, for fan-in greater
than 6
Input Pattern Ordering
(2-input NAND)
 leakage current in a
stack is ‘almost’
independent of ordering
for a constant number
of ‘off’ transistors


the leakage power is
the same for inputs
“0,1” and “1,0” at 0.35u
the difference
increases as the DSM
process shrinks
Input Pattern Ordering
(higher order gates)
 The leakage power varied
considerably for patterns
containing only one ‘zero’
 For NMOS stacks (NAND
gates):
 a ‘zero’ closest to the
output gives the largest IS1
 a ‘zero’ closest to ground
gives the smallest IS1
 For PMOS stacks (NOR
gates):
 a ‘one’ closest to the output
gives the largest IS1
 a ‘one’ closest to Vdd gives
the smallest IS1