Transcript Introduction to VHDL Multiplexers Discussion D1.1

Introduction to VHDL
Multiplexers
Discussion D1.1
Multiplexers
A multiplexer is a digital switch
2n
inputs
X(0, 2n -1)
MUX
n control lines
s( 0, n-1)
1 output, Z = X(s)
Multiplexers
C0
C1
C2
C3
4x1
MUX
s1 s0
Y
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0
0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A multiplexer is a
digital switch
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
0 1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1
0
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
Multiplexers
4x1
MUX
C0
C1
C2
C3
Y
s1 s0
1
1
s1 s0
Y
0
0
1
1
C0
C1
C2
C3
0
1
0
1
A 2 x 1 MUX
A
2x1
MUX
B
s0
Z
s0
Z
0
A
1
B
Behavior
if (s0 = '0') then
Z := A;
else
Z := B;
end if;
if (s0 =
A :=
B :=
else
A :=
B :=
end if;
'0') then
C0;
C2;
A 4 x 1 MUX
C1;
C3;
if (s1 = '0') then
if (s0 = '0') then
Z := C0;
else
Z := C1;
end if;
else
if (s0 = '0') then
Z := C2;
else
Z := C3;
end if;
end if;
C0
2x1
MUX
C1
A
2x1
MUX
s0
Z
B
C2
2x1
MUX
s1
C3
s0
if (s1 = '0') then
Z := A;
else
Z := B;
end if;
A 4 x 1 MUX
s1 s0
C0
C1
C2
4x1
MUX
C3
s1 s0
Z
0
0
1
1
0
1
0
1
Z
C0
C1
C2
C3
case s is
when
when
when
when
end case;
"00"
"01"
"10"
others
=>
=>
=>
=>
Z
Z
Z
Z
<=
<=
<=
<=
C0;
C1;
C2;
C3;
n-line 2-to-1 Multiplexer
a(n-1:0)
b(n-1:0)
n-line
2 x 1 MUX
sel
y(n-1:0)
sel
0
1
y
a
b
An n-line 2 x 1 MUX
a(n-1:0)
library IEEE;
use IEEE.std_logic_1164.all;
b(n-1:0)
n-line
2x1
MUX
y(n-1:0)
entity mux2g is
sel
generic (width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end mux2g;
Entity
library IEEE;
use IEEE.std_logic_1164.all;
Each entity must
begin with these
library and use
statements
generic statement defines
width of bus
entity mux2g is
generic (width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end mux2g;
port statement defines
inputs and outputs
Entity
library IEEE;
use IEEE.std_logic_1164.all;
Mode: in or out
entity mux2g is
generic (width:positive);
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end mux2g;
Data type: STD_LOGIC,
STD_LOGIC_VECTOR(width-1 downto 0);
Standard Logic
library IEEE;
use IEEE.std_logic_1164.all;
type std_ulogic is ( ‘U’, -- Uninitialized
‘X’ -- Forcing unknown
‘0’ -- Forcing zero
‘1’ -- Forcing one
‘Z’ -- High impedance
‘W’ -- Weak unknown
‘L’ -- Weak zero
‘H’ -- Weak one
‘-’); -- Don’t care
Standard Logic
Type std_ulogic is unresolved.
Resolved signals provide a mechanism
for handling the problem of multiple
output signals connected to one signal.
subtype std_logic is resolved std_ulogic;
Architecture
architecture mux2g_arch of mux2g is
begin
mux2_1: process(a, b, sel)
begin
a(n-1:0)
if sel = '0' then
y <= a;
b(n-1:0)
else
y <= b;
end if;
end process mux2_1;
end mux2g_arch;
n-line
2x1
MUX
y(n-1:0)
sel
Note: <= is signal assignment
Architecture
entity name
process sensitivity
architecture mux2g_arch of mux2g is
list
begin
mux2_1: process(a, b, sel)
begin
if sel = '0' then
y <= a;
else
y <= b;
end if;
end process mux2_1;
end mux2g_arch;
Note begin…end
in architecture
Sequential statements
(if…then…else) must
be in a process
Note begin…end
in process
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
Top-level design
for Lab 1
entity Lab1 is
port(
SW : in STD_LOGIC_VECTOR(7 downto 0);
BTN0 : in STD_LOGIC;
LD : out STD_LOGIC_VECTOR(3 downto 0)
);
end Lab1;
SW(7:4)
SW(3:0)
a 4-line
2-to-1
b MUX
sel
BTN0
y
LD(3:0)
architecture Lab1_arch of Lab1 is
component mux2g
generic(
width : POSITIVE);
port(
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
sel : in std_logic;
y : out std_logic_vector((width-1) downto 0));
end component;
constant bus_width: integer := 4;
begin
mux2: mux2g generic map(width => bus_width) port map
(a => SW(7 downto 4),b => SW(3 downto 0), sel => BTN0, y => LD);
end Lab1_arch;
SW(7:4)
SW(3:0)
a 4-line
2-to-1
b MUX
sel
BTN0
y
LD(3:0)
Lab1.ucf
#PACE: Start
NET "BTN0"
NET "LD<0>"
NET "LD<1>"
NET "LD<2>"
NET "LD<3>"
NET "SW<0>"
NET "SW<1>"
NET "SW<2>"
NET "SW<3>"
NET "SW<4>"
NET "SW<5>"
NET "SW<6>"
NET "SW<7>"
of PACE I/O Pin Assignments
LOC = "M13" ;
LOC = "K12" ;
LOC = "P14" ;
LOC = "L12" ;
LOC = "N14" ;
LOC = "F12" ;
LOC = "G12" ;
LOC = "H14" ;
LOC = "H13" ;
LOC = "J14" ;
LOC = "J13" ;
LOC = "K14" ;
LOC = "K13" ;
architecture Lab1_arch of Lab1 is
component mux2g
generic(
width : POSITIVE);
port(
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
sel : in std_logic;
y : out std_logic_vector((width-1) downto 0));
end component;
begin
constant bus_width: integer := 4;
mux2: mux2g generic map(width => bus_width) port map
(a => SW(7 downto 4),b => SW(3 downto 0), sel => BTN0, y => LD);
end Lab1_arch;
An n-line 4 x 1 multiplexer
a(n-1:0)
b(n-1 :0)
c(n-1 :0)
d(n-1 :0)
8-line
4x1
MUX
sel(1:0)
y(n-1 :0)
Sel
“00”
“01”
“10”
“11”
y
a
b
c
d
An 8-line 4 x 1 multiplexer
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4g is
generic(width:positive := 8);
port (
a: in STD_LOGIC_VECTOR (width-1 downto 0);
b: in STD_LOGIC_VECTOR (width-1 downto 0);
c: in STD_LOGIC_VECTOR (width-1 downto 0);
d: in STD_LOGIC_VECTOR (width-1 downto 0);
sel: in STD_LOGIC_VECTOR (1 downto 0);
y: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end mux4g;
Example of case statement
architecture mux4g_arch of mux4g is
begin
Note implies operator =>
process (sel, a, b, c, d)
begin
case sel is
Sel
y
when "00"
=> y <= a;
“00”
a
when "01"
=> y <= b;
“01”
b
when "10"
=> y <= c;
when others => y <= d;
“10”
c
end case;
“11”
d
end process;
end mux4g_arch;
Must include ALL possibilities
in case statement