Semiconductor Device Modeling and Characterization EE5342, Lecture 30 Spring 2003

Professor Ronald L. Carter [email protected]

http://www.uta.edu/ronc/ L30 01May03 1

Gummel-Poon Static npn Circuit Model

C R C Intrinsic Transistor B R BB B’ I LC I LE I BR I BF I CC - I EC = {IS/Q B }* {exp(v BE /NFV t ) exp(v BC /NRV t )} R E E L30 01May03 2

Gummel Poon npn Model Equations

I

BF

= IS expf(v

BE

/NFV

t

)/BF I

LE

= ISE expf(v

BE

/NEV

t

) I

BR

= IS expf(v

BC

/NRV

t

)/BR I

LC

= ISC expf(v

BC

/NCV

t

) I CC - I EC = IS(exp(v BE /NFV t - exp(v BC /NRV t )/Q B Q

B

= {  + IBR/IKR) [  ]

1/2

+ (BF IBF/IKF + BR }  (1 - v

BC

/VAF - v

BE

/VAR )

-1

L30 01May03 3

L30 01May03

VBIC Model Overview

[5]  Self-heating effects included  Improved Early effect modeling  Quasi-saturation modeling  Parasitic substrate transistor modeling  Parasitic fixed (oxide) capacitance modeling  An avalanche multiplication model included  Base current is decoupled from collector current 4

CAD Tools Support for VBIC

• Hspice [4]   Does not support PNP device Does not scale with “Area” and “M” terms • Spectre [5]   Support both NPN and PNP devices scale with “Area” and “M” term • HPADS  No temperature nodes (“dt” and “tl”), so unable to simulate thermal coupling effects L30 01May03 5

Temperature Designations for VBIC Parameters Description Temperature rise of the device from ambient Ambient temp.

Parameters measurement temperature Spectre [4] Name Default trise 0 temp tnom 27 27 Hspice [5] Name Default dtemp 0 temp tnom tref 25 25 27 L30 01May03 6

Using VBIC in Spectre

[5]

Name c b e [s] [dt] [tl] ModelName parameter=value ...

• Selft=1 and Rth>0 to enable Self-heating • 1 volt at the temperature nodes = 1 degree in temperature • “ tl ” node represents the initial local temperature of device which

always

corresponds to

trise+temp

• “ dt ” node represents the rise above trise+temp caused by thermal dissipation, whose value equals

V(dt)-V(tl)

• Device temperature=V(dt)-V(tl)+trise+temp L30 01May03 7

Using VBIC in Cadence

• Need explicit external temperature nodes in the symbol to model inter-device thermal coupling by  Connecting thermal network between “dt” nodes, or  Adding VCVS between “tl” and “tlr” node • Customized VBIC 6-terminal (5-pin) symbol L30 01May03 8

Model Conversion

• Most BJTs are defined with SGP model • A conversion from SGP to VBIC is needed • Only approximate conversion is possible • Some parameters are left unmapped such as R th C th • Two approaches are provided   and Manual conversion — done empirically and need Local Ratio Evaluation [2] Program conversion — “official” program sgp_2_vbic [3] L30 01May03 9

Parameters Mapping by sgp_2_vbic VBIC mapping Rcx Rci Rbx Rbi Re Is Rc 0 Rbm Rb-Rbm Re Is Nf Nr Fc Cje Pe Me Cjc Cjep Pc Nf Nr Fc Cje Vje Mje Cjc·Xcjc Vjc VBIC mapping VBIC mapping Mc Cjcp Ps Ms Nei Iben Nen Ibei Ibci Nci Ibcn Ncn Ikf Cjc(1-Xcjc) Ikr Tf Mjc Cjs Vjs Mjs Nf Ise Ne Is/Bf Is/Br Nr Isc Nc Ikf Ikr Tf Xtf Vtf Itf Tr Td Ea Eaie Eaic Eane Eanc Xis Xii Xin Kfn Afn Xtf Vtf Itf Tr  Tf·Ptf/180 Eg Eg Eg Eg Eg Xti Xti-Xtb Xti-Xtb Kf Af      

q bc F

 Early Effect model is different  Need Vbe, Vbc to solve the 3 equations below

g g



I I F O C e R o g o F q bc R

 

C F bc

/ 1

I c

1  

V V F be R be R q be

 / / 1 1

F q be g o R

/ /

V AR V AR

/

V AF



V F bc V AR



C be R I e V R bc

       / /

V V

     

V V

1 1

EF ER

     

AF AF

      1 1    L30 01May03 10

L30 01May03 11

Heterojunction Electrostatics E C,n E F,n E V,n q f n L30 01May03 -x n D E V 0 D E C q f p x p E o E C,p E F,p E V,p 12

Poisson’s Equation

dE dx x   n  n  qN D  n E x dE dx x   p  p   qN A  p  E x dx  V bi , n  E x dx -x n  V bi , n L30 01May03 x x p Continuity  n E x  x  0 eqn at x     p E x  x   0 0   13

Heterojunction electronics

Charge neutrality , qN d x n  qN a x p V bi q f n  E c    f  p E o   q f n E f , n   E f , n q  n E v , n  f n     E f , n kT E g , n  kT  ln  q  n  N c /   E f , n  N d  E c    E v , n  ln  N v / p no  E f , n , p no   n i 2 L30 01May03 / N d 14

Heterojunction electronics (cont)

q f p  E c    E o E f , p    q f p E f , p   q  E v , p p   E f ,  kT p E g ,  ln p  q   N c  p /  E f ,  kT ln  N v /  n po  E c   E f , , n po p  p  E v , p  , N a  ,  , n i 2 / N a c.f.

8.39

& 8.40

in text.

. L30 01May03 15

Heterojunction electronics (cont)

e.g.

8.39

qV bi  D E v  kT ln     p p po no N N v , n v , n     , p po  N a , and p no  n i 2 /N d . Since hole injection is important, and the appropriat e barrier is D E v then L30 01May03 this is the appropriat e form.

16

Heterojunction depletion widths

W  x n  x p    2  n qN d , n  p V bi N a , p    N d , n n N d , n  N a , p   2  p N a , p    x n  qN d , n 2  n   n  p V bi N a , p N d , n   p N a , p  x p  qN a , p 2   n  n  p V bi N N d , n  d , n  p N a , p    L30 01May03 17

Final Exam

• Review a paper on “Device Parameter Extraction”.

• Paper to be reviewed will be posted Monday, May 5, 2003 • Comment on Device Physics used.

• Critique the extraction procedures – Assumptions – Consistency of method w.r.t. assumptions • One page solution due 11 AM, Thur., May 8 L30 01May03 18

References

• • • • • Fujiang Lin, et al, “Extraction Of VBIC Model for SiGe HBTs Made Easy by Going Through Gummel-Poon Model”, from http://eesof.tm.agilent.com/pdf/VBIC_Model_Extractio n.pdf

http://www.fht-esslingen.de/institute/iafgp/neu/VBIC/ Avanti Star-spice User Manual, 04, 2001.

Affirma Spectre Circuit Simulator Device Model Equations

Zweidinger, D.T.; Fox, R.M., et al, VCVS representation 1198 -1206 ” “ Equivalent circuit modeling of static substrate thermal coupling using , Solid-State Circuits, IEEE Journal of , Volume: 2 Issue: 9 , Sept. 2002, Page(s): L30 01May03 19