Transcript Power Supply Control at NSLS-II Yuke Tian Control Group, NSLS-II, BNL

Power Supply Control at NSLS-II
Yuke Tian
Control Group, NSLS-II, BNL
(May 1, 2009 EPICS Collaboration Meeting, Vancouver)
Outline
1. Power supply control in accelerator
2. NSLS-II power supply control system
3. Synchronism, deterministic and reliability in NSLS-II power supply control
4. Summary
EPICS Collaboration Meeting, Vancouver 2009
Power supply control in accelerator: magnets at NSLS-II
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FC
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Dipole
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Dipole
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Standards for Main Dipole Magnet
FC
Standards for Fast Corrector Magnet
Standards for Quardupole Magnet
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Standards for Sextupole Magnet
Standards for Slow Corrector Magnet
EPICS Collaboration Meeting, Vancouver 2009
Power supply control in accelerator
• Power supply system functions
 Establish particle orbit
 Orbit correction
 Beam-based alignment
 Tune adjustment
 Cure of chromaticity
 Response matrix measurement
 Power supply analysis
• Power supply system performance requirements and NSLS-II solutions
 Reliability: power supply causes most of the failure time
1) Failures caused by harsh environments: moisture, dust, temperature etc.
NSLS-II solutions: temperature controlled racks.
2) Power supply control system failure: communication, IC parts failure etc.
NSLS-II solutions: redundant SDI links; Built-in diagnostic functions.
 Synchronization: power supply system needs to be synchronous with other
accelerator subsystems to perform various functions. Usually the
synchronization is done through timing system.
NSLS-II solutions: fully synchronous system including BPMs, cell
controllers and power supply controllers.
EPICS Collaboration Meeting, Vancouver 2009
Power Supply Control at NSLS-II: overview
Events/ / Timing Data
Fast Orbit Feedback Synchronous Bus
Ethernet – EPICS Channel Access Protocol
C
P
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PS control
For one cell
Cell
Controller
FC1
RFBPM 1
FC2
RFBPM 2
FC3
DCPS 01
DCPS 02
RFBPM 8
SC1
SC2
XRay BPM1
XRay BPM2
XRay BPM4
SC6
DCPS 39
DC Power Supply Controllers
For Multipole Magnets
XRay BPM4
Correctors
EPICS Collaboration Meeting, Vancouver 2009
Power Supply Control at NSLS-II: overview
NSLS-II Power Supply Control System
EPICS Collaboration Meeting, Vancouver 2009
NSLS-II Power Supply Control System: Cell Controller
Detailed Structure of Cell Controller
EPICS Collaboration Meeting, Vancouver 2009
NSLS-II Power Supply Control System: PSC, PSI, Regulator
Power Supply Control System
EPICS Collaboration Meeting, Vancouver 2009
NSLS-II Power Supply Control System: PSC
Power Supply Controller (PSC)
EPICS Collaboration Meeting, Vancouver 2009
NSLS-II Power Supply Control System: PSI
Power Supply Interface (PSI)
EPICS Collaboration Meeting, Vancouver 2009
NSLS-II Power Supply Control System: Regulator
Current Regulator Module
EPICS Collaboration Meeting, Vancouver 2009
Synchronism, Deterministic and Reliability in NSLS-II power supply control
Clock Domains In Accelerators
EPICS Collaboration Meeting, Vancouver 2009
Synchronism, deterministic and reliability in NSLS-II power supply control
• Synchronism in NSLS-II
 125MHz clock (in sync with master oscillator) and fiducia will be
distributed. We already have a very fine, low jitter clock. We can
synchronize all circuit with this RF clock. We can timestamp every event
with 8ns resolution. All the systems are talking with the same clock.
 Traditional power supply control system receive a trigger pulse from
timing system and use local oscillators to drive the DAC, ADC etc.
NSLS-II solutions: pushing synchronism to power supply control. The
DAC, ADC and FPGA are synchronous with RF main oscillator. The
local oscillators are for back up in case the RF main oscillator is not
available.
EPICS Collaboration Meeting, Vancouver 2009
Synchronism, deterministic and reliability in NSLS-II power supply control
Pushing Synchronism to Power Supply Control at NSLS-II
EPICS Collaboration Meeting, Vancouver 2009
Synchronism, deterministic and reliability in NSLS-II power supply control
Latency of Power Supply SDI Link
PS setpoint
PS readback
PS for fast
correctors
Total data for FOFB
100Mbit/s SDI
link
2 18-bit DAC
8-bit command
10 16-bit ADC
(20bytes)
6 PS
Setpoints: 7x6=42 byte
Readback: 20 byte
(294*8)/100Mb
= 24us
(7 bytes/PS)
Assume payload: 42 bytes
42 *7 =294 Byte
EPICS Collaboration Meeting, Vancouver 2009
Summary
• At NSLS-II, power supplies and the power supply control systems are
designed with goals of high reliability, easy for diagnostics, and easy for
integration.
• At NSLS-II, we are design a open source communication interface for
power supply control system. It offers more advantages than other
communications interface such as RS232, RS485, CAN etc.
• At NSLS-II, we are pushing synchronism to power supply control level. So,
all the subsystems (BPM, PS, LLRF etc) are all synchronized, many
accelerator applications can benefit from this synchronism.
 Fast orbit feedback system
1) Synchronous distribution of BPM data (by SDI between cells)
2) Matrix math and regulation (done with the same clock)
3) Corrector PS actions (by SDI between PS controller)
 Response matrix measurement:
1) Synchronous kick one or more magnets (by SDI between PS
controller)
2) Synchronous measurement of the BPM data (by GigE interface)
 Other applications: tune measurements, synchronous PS ramping etc.
EPICS Collaboration Meeting, Vancouver 2009
Acknowledgement
Wing Louie (BNL)
John Ricciardelli (BNL)
George Ganetis (BNL)
Larry Doolittle (LBNL)
Bob Dalesio (BNL)
Carlos Serrano (LBNL)
Thank you !
EPICS Collaboration Meeting, Vancouver 2009