Transcript Document 7379341

Wireless Communication Extensions
for DSPs and
General Purpose Processors
Sridhar Rajagopal
COMP 625
April 17, 2000
Motivation
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Wireless, the next wave after Multimedia
Highly Compute-Intensive Algorithms
Real-Time Requirements
Design based on Time-to-Market
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Outline
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Processor Core with Reconfigurable Support
Permutation Based Interleaved Memory
Processor Architecture -EPIC
Instruction Set Extensions
Truncated Multipliers
Software Support Needed
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Characteristics of Wireless Algorithms
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Massive Parallelism
Bit-level Computations
Matrix Based Operations
Memory Intensive
Complex-valued Data
Approximate Computations
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What’s wrong with Current
Architectures for these applications?
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Problems with Current Architectures
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UltraSPARC, C6x, MMX, IA-64
Not enough MIPs/FLOPs
Unable to fully exploit parallelism
Bit Level Computations
Memory Bottlenecks
Specialized Instructions for Wireless Communications
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Why Reconfigurable
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Adapt algorithms to environment
Seamless and Continuous Data Processing during Handoffs
Home Area
Wireless LAN
High Speed
Office Wireless
LAN
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Outdoor CDMA
Cellular
Network
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Reconfigurable Support
OSI
Layers
3-7
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User Interface
Translation
Synchronization
Transport
Network
OSI
Layer
2
Data Link Layer
(Converts Frames
to Bits)
OSI
Layer
1
Physical Layer
(hardware;
raw bit stream)
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Different Protocols
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MPEG-4, H.723 - Voice,Multimedia
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Convolutional,Turbo - Channel Coding
Source Coding
Channel Coding
Source
Channel
Multiuser
Channel
Decoding
Decoding
Detection
Estimation
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A New Architecture
Processor
Core
(GPP/DSP)
Cache
Main
Memory
Q
Q
Crossbar
Reconfigurable
Real-Time
I/O
Logic
Bit Stream
RF Unit
Add-on PCMCIA
Network Interface Card
Processor
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Why Reconfigurable
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Process initial bit level computations
Optimize for fast I/O transfer
Reconfigurable
Real-Time
I/O
Logic
Bit Stream
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RF Unit
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Reconfigurable Support
2 64-bit data buses
1 64-bit address bus
Control
Blocks
Boolean
Fast I/O
Configuration
64-bit
Datapath
values
Caches Sequencer
GARP Architecture at UC,Berkeley
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Reconfigurable Support
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Wide Path to Memory
– Data Transfer
– Minimize Load Times
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Configuration Caches
– Recently Displaced Configurations(5 cycles)
– Can hold 4 full size Configurations
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Independent Execution
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Reconfigurable Support
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Access to same Memory System as Processor
– Minimize overhead
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When idle
– Load Configurations
– Transfer Data
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Operation
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Load Configuration
– If in configuration cache, minimal time
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Copy initial data with coprocessor move instructions
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Start execution
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Issue wait that interlocks while active
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Copy registers back at kernel completion
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Memory Interface
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Access to Main Memory and L1 Data Cache
– Large, fast Memory Store
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Memory Prefetch Queues for Sequential Accesses
– Read aheads and Write Behinds
Instruction Cache
Processor
Core
L1 Data
Cache
(GPP/DSP)
Q
Main
Memory
Q
Crossbar
FPGA
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Permutation Based Interleaved
Memory (PBI)
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High Memory Bandwidth Needed
Stride-Insensitive Memory System for Matrices
Multiple Banks
Sustained Peak Throughput (95%)
L1 Data
Cache
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Main
Memory
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PBI Scheme
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N- address length
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M = 2n Banks
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2N-n words in each bank
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To access a word,
– n-bit bank number
– N-n bit address (high-order)
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Calculation of the n-bit Bank Number
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Calculate Bank Number
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Use all N bits to get n-bit vector
Y = A X , A = n*N matrix of 0’s & 1’s
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Y = AhXh + Al Xl (N-n,n) [Al -rank n]
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N-bit parity circuit with logkN levels of XOR gates (k-Fanin)
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N-bit address
Parity Ckt.
Parity Ckt.
Parity Ckt.
Row 0 of A
Row 1 of A
Row n-1 of A
n parity bit signals
Decoder
2n bank select signals
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Interleaved Memory Model
Input Buffers
Address Source
Memory Banks
M(0)
M(1)
Data Sink
M(M-1)
Data Sequencer
Output Buffers
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Processor Core
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64-bit EPIC Architecture with Extensions(IA-64/C6x)
Statically determined Parallelism;exploit ILP
Execution Time Predictability
Processor
Core
(GPP/DSP)
Cache
Q
Q
Crossbar
FPGA
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EPIC Principle
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Explicitly Parallel Instruction Computing
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Evolution of VLIW Computing
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Compiler- Key role
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Architecture to assist Compiler
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Better cope with dynamic factors
– which limited VLIW Parallelism
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Aspects of EPIC
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Designing Plan of Execution(POE) at Compile Time
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Permitting Compiler to play Statistics
– Conditional Branches, Memory references
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Communicating POE to the hardware
– Static Scheduling
– Branch information
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Architecture Features in EPIC
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Static Scheduling
– MultiOP
– Non-Unit Assumed Latency (NUAL)
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The Branch Problem
– Predicated Execution
– Control Speculation
– Predicated Code Motion
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The Memory Problem
– Cache Specifiers
– Data Speculation
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Instruction Set Extensions
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To accelerate Bit level computations in Wireless
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Real/Complex Integer - Bit Multiplications
– Used in Multiuser Detection, Decoding
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Bit - Bit Multiplications
– Used in Outer Product Updates
– Correlation, Channel Estimation
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Complex Integer-Integer Multiplications
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Useful in other Signal Processing applications
– Speech, Video,,,
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Architecture Support
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Support via Instruction Set Extensions
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Minimal ALU Modifications necessary
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Transparent to Register Files/Memory
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Additional 8-bit Special Purpose Registers
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Integer - Bit Multiplications
D[I] = D[I] + b[J]*C[j]
Eg: Cross-Correlation
64-bit Register A
+/-
+/-
64-bit Register C
+/-
8-bit Register b
64-bit Register D
Register Renaming?
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8-bit to 64-bit conversions
1.1
D = D + b*bT
Eg: Auto-Correlation
1.2
2.1
b1 = b(1:8),b(1:8),….b(1:8) b2 = b(1)b(1)……b(8)b(8)
8-bit Register b
64-bit Register A
b(1)..b(8)
b(1) b(2)
b(7) b(8)
b(1)..b(8)
b(1) b(1)
b(8) b(8)
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Bit-Bit Multiplications
D = D + b*bT
Eg: Auto-Correlation
b1*b2
Bit-Bit Multiplications
64-bit Register A = b1
B1 B2 B1*B2
0
0
1
0
1
0
1
0
0
1
1
1
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64-bit Register B=b2
Ex-NOR
64-bit Register C=b1*b2
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Increment/Decrement
D = D + b*bT
Eg: Auto-Correlation
64-bit Register D
1
+/-
+/-
+/-
8-bit Register b1*b2
64-bit Register (D+b1*b2)
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Complex-valued Data Processing
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Is it easy to add ?
Is this worth an additional ALU Support ?
Typically supported by Software!
?
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Truncated Multipliers
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Many applications need approximate computations
Adaptive Algorithms :Y = Y + mu*(Y*C)
Truncate lower bits
Truncated Multipliers - half the area/half the delay
Can do 2 truncated multiplies in parallel with regular
ALU Multipliers
Truncated
Multiplier 1
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Multiplier 2
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Multiplier
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Software Support
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Greater Interaction between Compilers and Architectures
– EPIC
– Reconfigurable Logic
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Compiler needs to find and exploit bit level computations
Reconfigurable Logic Programming
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Area Estimates
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Area increase by 20% over a IA-64 architecture size due
to reconfigurable Support
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Instruction Set extensions need min hardware support
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Parallel Interleaved Memory Banks will need larger area
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Other Uses
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Reconfigurable Logic
– For accelerating loops of general purpose processors
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Bit Level Support
– For other voice, video and multimedia applications
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Conclusions
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Processor Core with Reconfigurable Support developed for
Wireless Applications
Instruction Set Extensions added for accelerating
performance of the algorithms
Integration of Wireless Appliances with General Purpose
Processors
Great Impact on Performance of Wireless Algorithms
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Future Work
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Simulations for finding performance improvements
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Other Processor Architectures
– Bit Slice Architectures
– Out-of-order
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References
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The GARP Architecture and C Compiler
– T.C. Callahan,J.R.Hauser,J.Wawrzynek, IEEE Computer,April 2000, pp62-69
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http://brass.cs.berkeley.edu
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EPIC:Explicitly Parallel Instruction Computing
– M.S.Schlansker,B.R.Rau, IEEE Computer, Feb 2000, pp 37-45
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High-Bandwidth Interleaved Memories for Vector
Processors - A Simulation Study
– G.S.Sohi, IEEE Transactions on Computers, Vol.42,No.1,Jan 1993,pp34-44
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Acknowledgements
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Vijay Pai
Partha Ranganathan
Joseph Cavallaro
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