Transcript Lecture 2 CMOS Processing & Fabrication Pradondet Nilagupta

Lecture 2
CMOS Processing &
Fabrication
Pradondet Nilagupta
[email protected]
Department of Computer Engineering
Kasetsart University
Acknowledgement

This lecture note has been summarized from
lecture note on Introduction to VLSI Design,
VLSI Circuit Design all over the world. I can’t
remember where those slide come from.
However, I’d like to thank all professors who
create such a good work on those lecture
notes. Without those lectures, this slide can’t
be finished.
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N Transistor Structure Review
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P Transistor Structure Review
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Semiconductor Review
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Create by doping a pure silicon crystal
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n-type semiconductor (n or n+)
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Diffuse impurity into crystal lattice
Changes the concentration of carriers
 Electrons
 Holes
More doping -> more carriers available
Majority carrier: electrons
Typical impurity: Arsenic (Column V)
p-type semiconductor (p or p+)
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n+
n
p+
Majority carrier: holes
Typical impurity: Boron (Column III)
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Other key working materials
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Insulator - Silicon Dioxide (SiO2)
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Polysilicon - polycrystalline silicon
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Used to insulate transistor gates (thin oxide)
Used to insulate layers of wires (field oxide)
Can be grown on Silicon or Chemically Deposited
Key material for transistor gates
Also used for short wires
Added by chemical deposition
Metal - Aluminum (…and more recently Copper)
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Used for wires
Multiple layers common
Added by vapor deposition or “sputtering”
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CMOS Processing
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Wafer Processing
Photolithography
Oxide Growth & Removal
Material Deposition & Removal
Diffusion of Impurities
Putting it all together
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A View of the Cleanroom
AMD’s Dresden Fab - Source: AMD Corporation www.amd.com
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Creating Wafers - Czochralski
Method
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Start with crucible of
molten silicon
(≈1425oC)
Insert crystal seed in
melt
Slowly rotate / raise
seed to form single
crystal boule
After cooling, slice
boule into wafers &
polish
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Crucible
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Molten
Silicon
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Definitions
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Wafer – a thin circular silicon
Each wafer holds hundreds of dies
Transistors and wiring are made from many layers
(usually 10 – 15) built on top of one another
 the first half-dozen or so layers define transistors
 the second define the metal wires between transistors
Lambda () – the smallest resolvable feature size
imprinted on the IC;
it is roughly half the length of the smallest transistor
 0.2m IC – the smallest transistors are
approximately 0.2m in length (= 0.1m)
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Wafer Structure
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Current production:
200mm (10”)
Newest technology:
300mm (12”)
Die - Single IC chip
300mm wafer
Image Source: Intel Corporation
www.intel.com
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Processing Wafers
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All dice on wafer processed simultaneously
Each mask has one image for each die
The basic approach:
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Add & selectively remove materials
Metal - wires
 Polysilicon - gates
 Oxide
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Selectively diffuse impurities
Photolithography is the key
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Fabrication processes
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IC built on silicon substrate:
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some structures diffused into substrate;
other structures built on top of substrate.
Substrate regions are doped with n-type and
p-type impurities. (n+ = heavily doped)
Wires made of polycrystalline silicon (poly),
multiple layers of aluminum (metal).
Silicon dioxide (SiO2) is insulator.
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Photolithography
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Coat wafer with photoresist
(PR)
Shine UV light through
mask to selectively expose
PR
Use acid to dissolve
exposed PR
Now use exposed areas for
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UV Light
Mask
Photoresist
Wafer
Selective doping
Selective removal of material
under exposed PR
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Adding Materials
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Add materials on top of
silicon
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Added Material
(e.g. Polysilicon)
Polysilicon
Metal
Oxide (SiO2) - Insulator
Silicon
Methods
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Chemical deposition
Sputtering (Metal ions)
Oxidation
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Oxide (Si02) - The Key Insulator
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Thin Oxide
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Add using chemical deposition
Used to form gate insulator & block active areas
Field Oxide (FOX) - formed by oxidation
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Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)
Used to insulate non-active areas
SiO2 Thin Oxide
FOX
Silicon Wafer
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SiN / SiO2
FOX
Silicon Wafer
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Patterning Materials using
Photolithography
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Add material to wafer
Coat with photoresist
Selectively remove
photoresist
Remove exposed
material
Remove remaining PR
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Added Material
(e.g. Polysilicon)
Silicon
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Diffusion
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Introduce dopant via
epitaxy or ion implant
e.g. Arsenic (N), Boron
(P)
Allow dopants to diffuse
at high temperature
Block diffusion in
selective areas using
oxide or PR
Diffusion spreads both
vertically, horizontally
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Blocking Material
(Oxide)
Diffusion
Silicon
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CMOS Well Structures
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Need to accommodate both N, P transistors
Must implement in separate regions - wellls
(tubs)
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N-well
P-well
Alternate approach: Silicon on Insulator (SOI)
n well
p well
p substrate
n substrate
n-well
p-well
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n tub
p tub
twin-tub
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n epi
p epi
insulator
SOI
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Detailed View - N-Well Process
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Overall chip doped as p substrate, tied to
GND
Selected well areas doped n, tied to VDD
Gnd
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VDD
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CMOS Processing - Creating an
Inverter
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Substrate
Well
Active Areas
Gates
Diffusion
Insulator
Contacts
Metal
P substrate
n well
wafer
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CMOS Mask Layers
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Determine placement of
layout objects
Color coding specifies
layers
Layout objects:
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Rectangles
Polygons
Arbitrary shapes
Grid types
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Absolute (“micron”)
Scaleable (“lambda”)
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P substrate
n well
wafer
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Mask Generation
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Mask Design using Layout Editor
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Pattern Generator
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user specifies layout objects on different layers
output: layout file
Reads layout file
Generates enlarged master image of each mask layer
Image printed on glass reticle
Step & repeat camera
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Reduces & copies reticle image onto mask
One copy for each die on wafer
Note importance of mask alignment
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Simple cross section
SiO2
metal3
metal2
metal1
transistor
via
poly
n+
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p+
n+
substrate
substrate
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Transistor structure
n-type transistor:
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0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
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Metal Layers
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Current Trends in Fabrication
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Copper Interconnect
Low-k dielectric for interconnect
High-k dielectric for transistor gates
Optical problems (and attempted fixes)
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Copper interconnect
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Copper is a much better conductor than aluminum
But, it tends to chemically react w/ silicon, oxide
Fabrication of copper wires: “damascene” process
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Etch trenches in the surface where wires will be placed
Coat with “secret chemical” (isolates Cu, silicon, oxide)
Coat with layer of copper
Polish wafer to remove copper except in trenches
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Alternative Dielectrics
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Dielectric constant of SiO2: 3.9
Problem: want to minimize coupling
capacitance between wires
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Solution: “low-k” dielectrics (featured in 130nm
and below)
Proposed materials would have approx K=3
Problem: want to maximize electric field
under transistor gates
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Solution: “high-k” dielectrics (anticipated in 90nm
and below)
Proposed materials would have K>>4
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Optical Problems
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Most photolithography is done using UV with
248nm wavelength
BUT… current geometries << 248nm =>
interference problems
Fixes:
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Optical proximity correction (OPC)
Phase-shifting masks
Other light sources: 193nmUV, Extreme UV, XRays
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E-beam lithography
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Example - Phase Shifting Masks
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Normal mask - light spreads & overlaps
Phase shifting mask - cancels overlap
Drawback: requires 2 masks per litho. step
(Expensive)
Graphic source: Numerical Technologies www.numeritech.com
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After Fabrication- Testing and
Packaging
Figure Source: D. Patterson and J. Hennessey, Computer Organization and Design, Morgan Kafumann, 1996
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Fabrication Example - MOSIS
Tiny chip
Photo Source:
R. Feiller ‘02
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Fabrication services
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Educational services:
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U.S.: MOSIS
EC: EuroPractice
Taiwan: CIC
Japan: VDEC
Foundry = fabrication line for hire.
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Foundries are major source of fab capacity today.
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