Transcript Lecture 3 Transistors, Wires, & Parasitics Pradondet Nilagupta

Lecture 3
Transistors, Wires, &
Parasitics
Pradondet Nilagupta
[email protected]
Department of Computer Engineering
Kasetsart University
Acknowledgement

This lecture note has been summarized from
lecture note on Introduction to VLSI Design,
VLSI Circuit Design all over the world. I can’t
remember where those slide come from.
However, I’d like to thank all professors who
create such a good work on those lecture
notes. Without those lectures, this slide can’t
be finished.
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Where we are...

Last time:


CMOS Processing
Today:



Transistor Modes of Operation
More about Wires & Vias
Parasitics
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Roadmap for the term: major
topics









VLSI Overview
CMOS Processing & Fabrication
Components: Transistors, Wires, & Parasitics
Design Rules & Layout
Combinational Circuit Design & Layout
Sequential Circuit Design & Layout
Standard-Cell Design with CAD Tools & Verilog
Mixed Signal Concerns: D/A, A/D Conversion
Design Project: Complete Chip
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Review - Transistor Structure
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N Transistor Operation - Cutoff

Vgs << Vt : Transistor OFF


Majority carrier in channel (holes)
No current from source to drain
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N Transistor Operation Subthreshold

0 < Vgs < Vt : Depletion region



Electric field repels majority carriers (holes)
Depletion region forms - no carriers in channel
No current flows (except for leakage current)
VS =0
0<VGS <VT
source
VDS =0
drain
depletion region
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N Transistor Operation - ON

Vgs > Vt , VDS=0: Transistor ON




Electric field attracts minority carriers (electrons)
Inversion region forms in channel
Depletion region insulates channel from substrate
Current can now flow from drain to source!
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N Transistor Operation - Linear

Vgs > Vt , VDS <VGS -VT : Linear (Active) mode


Combined electric fields shift channel and
depletion region
Current flow dependent on VGS, VDS
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N Transistor Operation Saturation

Vgs > Vt , VDS >VGS -VT : Saturated mode



Channel “pinched off”
Current still flows due to electron drift
Current flow dependent on VGS
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P Transistor Operation


Opposite of N-Transistor
 Vgs >> Vt : Transistor OFF
 Majority carrier in channel (electrons)
 No current from source to drain
 0 > Vgs > Vt : Depletion region
 Electric field repels majority carriers (electrons)
 Depletion region forms - no carriers in channel
 No current flows (except for leakage current)
Vgs < Vt , VDS=0: Transistor ON
 Electric field attracts minority carriers (holes)
 Inversion region forms in channel
 Depletion layer insulates channel from substrate
 Current can now flow from source to drain!
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P Transistor Modes of Operation

Vgs <Vt , VDS >VGS -VT : Linear (Active) mode



Combined electric fields shift channel and
depletion region
Current flow dependent on VGS, VDS
Vgs < Vt , VDS <VGS -VT : Saturation mode



Channel “pinched off”
Current still flows due to hole drift
Current flow dependent on VGS
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N-type Transistor structure
n-type transistor:
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0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
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Transistor layout
n-type (tubs may vary):
L
w
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I-V Characteristics of MOS
Transistors
linear
saturation
saturation
p transistor
n transistor
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linear
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Ideal Transistor Equations


Cutoff Region:
Linear Region


(EQ 2-1)
Vgs < Vt I d  0
Vds < Vgs - Vt
1 W 
1 2 2
I d  k'
(Vgs  Vt )Vds  Vds


2 L
2
Saturated Region Vds ≥ Vgs - Vt
Id 
1 W
k' (Vgs  Vt ) 2
2 L
- Channel Length Modulation Parm.

(EQ 2-2)

1 W
2
(EQ 2-16) I d  k' (Vgs  Vt ) (1  Vds )
2 L
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More about Transistor Equations

More about k'





me
µ - effective surface mobility of carrier k' 
tox
e - permittivity of gate insulator
tox - thickness of gate insulator
Beta - a measure of gain
Important things to remember:


W
b  k
L
these equations are approximations
Use circuit simulator ( e.g. PSpice)
for more accurate modeling
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0.5 mm transconductances
From a MOSIS process:
 n-type:



kn’ = 73 mA/V2
Vtn = 0.7 V
p-type:


kp’ = 21 mA/V2
Vtp = -0.8 V
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Current through a transistor
Use 0.5 mm parameters. Let W/L = 3/2.
Measure at boundary between linear and
saturation regions.
 Vgs = 2V:
Id = 0.5k’(W/L)(Vgs-Vt)2= 93 mA

Vgs = 5V:
Id = 1 mA
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MOSFET gate as capacitor

Basic structure of gate is parallel-plate
capacitor:
gate
+
Vg
SiO2
tox
-
substrate
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Parallel plate capacitance

Formula for parallel plate capacitance:
Cox = eox / tox

Permittivity of silicon:
eox = 3.46 x 10-13 F/cm2

Gate capacitance helps determine charge in
channel which forms inversion region.
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Threshold voltage
Components of threshold voltage Vt:
 Vfb = flatband voltage; depends on difference
in work function between gate and substrate
and on fixed surface charge.
 s = surface potential (about 2f).
 Voltage on paralell plate capacitor.
 Additional ion implantation.
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Body effect



Reorganize threshold voltage equation:
Vt = Vt0 + Vt
Threshold voltage is a function of
source/substrate voltage Vsb.
Body effect  is the coefficienct for the Vsb
dependence factor.
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Example: threshold voltage of a
transistor
Vt0 = Vfb + s + Qb/Cox + VII
= -0.91 V + 0.58 V + (1.4E-8/1.73E-7) + 0.92 V
= 0.68 V
Body effect n = sqrt(2qeSiNA/Cox) = 0.1
Vt = n[sqrt(s + Vsb) - sqrt(s)]
= 0.16 V
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Channel length modulation
length parameter



 describes small dependence of drain
corrent on Vds in saturation.
Factor is measured empirically.
New drain current equation:
 Id

= 0.5k’ (W/L)(Vgs - Vt) 2(l -  Vds)
Equation has a discontinuity between linear
and saturation regions---small enough to be
ignored.
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Gate voltage and the channel
gate
source
current
drain
Vds < Vgs - Vt
Id
gate
source
current
drain
Vds = Vgs - Vt
drain
Vds > Vgs - Vt
Id
gate
source
Id
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Leakage and subthreshold
current


A variety of leakage currents draw current
away from the main logic path.
The subthreshold current is one particularly
important type of leakage current.
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Types of leakage current.







Weak inversion current (a.k.a. subthreshold
current).
Reverse-biased pn junctions.
Drain-induced barrier lowering.
Gate-induced drain leakage;
Punchthrough currents.
Gate oxide tunneling.
Hot carriers.
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Subthreshold current

Subthreshold current:



Isub = ke[(Vgs - Vt)/(S/ln 10)][1-e-qVds/kT]
Subthreshold slope S characterizes weak
inversion current.
Subthreshold current is a function of Vt.

Can adjust Vt by changing the substrate bias to
control leakage.
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The modern MOSFET
Features of deep submicron MOSFETs:
 epitaxial layer for heavily-doped channel;
 reduced area source/drain contacts for lower
capacitance;
 lightly-doped drains to reduce hot electron
effects;
 silicided poly, diffusion to reduce resistance.
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Circuit simulation


Circuit simulators like Spice numerically solve
device models and Kirchoff’s laws to
determine time-domain circuit behavior.
Numerical solution allows more sophisticated
models, non-functional (table-driven) models,
etc.
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Spice MOSFET models





Level 1: basic transistor equations of Section
2.2; not very accurate.
Level 2: more accurate model (effective
channel length, etc.).
Level 3: empirical model.
Level 4 (BSIM): efficient empirical model.
New models: level 28 (BSIM2), level 47
(BSIM3).
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Some (by no means all) Spice
model parameters






L, W: transistor length width.
KP: transconductance.
GAMMA: body bias factor.
AS, AD: source/drain areas.
CJSW: zero-bias sidewall capacitance.
CGBO: zero-bias gate/bulk overlap
capacitance.
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Threshold Voltage

Depends on gate capacitance, physical
constants

When Vsb=0:
Permittivity of SiO2 = 3.9e0
Oxide thickness (cm)

(EQN 2-4) Cox  e ox / xox

Qb
V

V



 VII
(EQN 2-5) t0
fb
s
C ox

(EQN 2-6)

(EQN 2-7)

(EQN 2-9)

(EQN 2-10) Qb  2qe siNas
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Vfb  gs  (Q f / Cox )
kT N a N dp 
 gs  
ln 

q  n 2 
i
kT N a
s  1 f 
ln
q
ni
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Adjustment - Ion Implant
Flatband voltage
Work function difference
Surface potential
Charge stored in depletion region
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Threshold Voltage - Body Effect

Vt increases when Vsb >0
Vt  Vt0  Vt

(EQN 2-11)
Vt0   n   s  Vsb   s 

(EQN 2-12)
 gs 
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2qe Si N a
C ox
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Subthreshold Current

Current can flow even when transistor is “off”

(EQ 2-17)
 Vg s Vt 

 S / ln10 



I sub  ke
1  ke
 qVd s / kT

S - subthreshold slope (measured in mV/decade)
q - charge of an electron
k - Boltzmann’s constant
T - temperature (Kelvin)
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Wires and Vias


Creating wires (review):
 Deposit insulator on chip (SiO2)
 Deposit conducting material on chip
 Selectively remove using photolithography
 Use multiple layers so wires can cross over each
other
Vias (Contacts) - Connect between layers
 “cuts” etched through insulator
 Metal connects between layers (with significant
resistance)
Wafer
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Wires and vias
metal 3
metal 2
vias
metal 1
poly
n+
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p-tub
poly
n+
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Metal migration (1/2)


Current-carrying capacity of metal wire
depends on cross-section. Height is fixed, so
width determines current limit.
Metal migration: when current is too high,
electron flow pushes around metal grains.
Higher resistance increases metal migration,
leading to destruction of wire.
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Metal Migration (2/2)



High current density can cause metal molecules to
move
Solution: size wires to keep current density with
recommended range (book: 1.5mA / µm width)
Also a problem in vias
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Metal migration problems and
solutions


Marginal wires will fail after a small operating
period—infant mortality.
Normal wires must be sized to accomodate
maximum current flow:
Imax = 1.5 mA/mm of metal width.

Mainly applies to VDD/VSS lines.
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Wiring Examples - Intel
Processes
k=3.6
Tungsten
Plugs
Intel 0.25µm Process (Al)
5 Layers - Tungsten Vias
Tungsten
Plugs
(Poly/diff. only)
Source: Intel Technical Journal 3Q98
Intel 0.13µm Process (Cu)
Source: Intel Technical Journal 2Q02
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Diffusion wire capacitance

Capacitances formed by p-n junctions:
sidewall
capacitances
depletion region
n+ (ND)
substrate (NA)
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bottomwall
capacitance
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Depletion region capacitance

Zero-bias depletion capacitance:


Depletion region width:


Cj0 = esi/xd.
xd0 = sqrt[(1/NA + 1/ND)2esiVbi/q].
Junction capacitance is function of voltage
across junction:

Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)
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Poly/metal wire capacitance

Two components:


parallel plate;
fringe.
fringe
plate
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Metal coupling capacitances

Can couple to adjacent wires on same layer,
wires on above/below layers:
metal 2
metal 1
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metal 1
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Example: parasitic capacitance
measurement


n-diffusion: bottomwall=2 fF, sidewall=2 fF.
metal: plate=0.15 fF,
fringe=0.72 fF.
1.5 mm
3 mm
0.75 mm
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1 mm
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2.5 mm
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Parastic Elements

So far, we’ve concentrated on getting circuit
elements that we want for digital design



Transistors
Wires
Parasitics - occur whether we want them or
not



Capacitors
Resistors
Transistors (bipolar and FET)
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Basic transistor parasitics (1/2)


Gate to substrate, also gate to source/drain.
Source/drain capacitance, resistance.
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Basic transistor parasitics (2/2)


Gate capacitance Cg. Determined by active
area.
Source/drain overlap capacitances Cgs, Cgd.
Determined by source/gate and drain/gate
overlaps. Independent of transistor L.


Cgs = Col W
Gate/bulk overlap capacitance.
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Capacitance (1/2)


Transistors
 Depends on area of transistor gate
 Depends on physical materials, thickness of insulator
 Given for a specific process as Cg
Diffusion to substrate
 Sidewall capacitance - capacitance from periphery
 bottomwall capacitance - capacitance to substrate
 See Eqns. 2-19 thru 2-22
 Given for a specific process as Cdiff,bot, Cdiff,side
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Capacitance (2/2)




Metal to substrate
 Parallel plate capacitance is dominant
 Need to account for fringing, too
Poly to substrate
 Parallel plate plus fringing, like metal
 Gotcha: don’t confuse poly over substrate with gate
capacitance
Sample parasitic values: Table 2-4, p. 85
Also important: capacitance between conductors
 Metal1-Metal1
 Metal1-Metal2
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Resistance




Depends on resistivity of material r (Rho)
Sheet resistance Rs = r /t see Table 2-4, p. 80
Resistance R = Rs * L / W
Corner approximation - count a corner as half a square
Example:
R = Rs(poly) * 13 + 2*(1/2) + 3*(1/2) squares
R = 4Ω/sq * 15.5 squares = 62Ω
Corner (1/2 Square)
1/2 Square
1/2 Square
Corner (1/2 Square)
Corner (1/2 Square)
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Wire resistance

Resistance of any size square is constant:
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Mean-time-to-failure


MTF for metal wires = time required for 50%
of wires to fail.
Depends on current density:




proportional to j-n e Q/kT
j is current density
n is constant between 1 and 3
Q is diffusion activation energy
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Skin effect


At low frequencies, most of copper
conductor’s cross section carries current.
As frequency increases, current moves to
skin of conductor.


Back EMF induces counter-current in body of
conductor.
Skin effect most important at gigahertz
frequencies.
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Skin effect, cont’d

Isolated conductor:

Conductor and ground:
Low frequency
Low frequency
High frequency
High frequency
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Skin depth

Skin depth is depth at which conductor’s
current is reduced to 1/3 = 37% of surface
value:




d = 1/sqrt(pf ms)
f = signal frequency
m = magnetic permeability
s = wire conducitvity
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Effect on resistance

Low frequency resistance of wire:


High frequency resistance with skin effect:


Rhf = 1/2 sd(w + t)
Resistance per unit length:


Rdc = 1/ s wt
Rac = sqrt(Rdc 2 + kRhf 2
Typically k = 1.2.
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Transistor gate parasitics

Gate-source/drain overlap capacitance:
gate
source
drain
overlap
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Transistor source/drain parasitics



Source/drain have significant capacitance,
resistance.
Measured same way as for wires.
Source/drain R, C may be included in Spice
model rather than as separate parasitics.
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Some Example Process Data



Book Table 2-4, p. 80 - 0.5µm process
AMI 1.5µm process (from www.mosis.org)
TSMC 0. 5µm process (from www.mosis.org)
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Parasitics - Final Notes

These are approximate calculations



Grossly oversimplified
Advanced CAD tools (e.g. field solver) needed for
accuracy
Process Variation

Parameter values are are not exact, but vary
depending on manufacturing, etc.
Typical process specifies a range for each parameter
 Must design chips to work for worst case - “process
corners”

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Example Problems Parasitic Calculation (1/10)
metal1
30
1=0.25µm
poly
ndiff
Rmetal1=?
Rpoly=?
Rndiff=?
Cmetal1=?
Cpoly=?
Cndiff=?
Note: see Table 2-4, p. 80 for parameters
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Example Problems Parasitic Calculation (2/10)
metal1
30
1=0.25µm
poly
ndiff
Rmetal1 = 30 / 3) * 0.08Ω/o = 0.8Ω
Cmetal1 = (30* 0.25µm/*(3* 0.25µm/*0.04fF/µm2 +
(30 + 330 + 3*0.25µm/* 0.09fF/µm
= 0.225fF + 1.485fF
= 1.71fF
Note: see Table 2-4, p. 80 for parameters
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Example Problems Parasitic Calculation (3/10)
metal1
30
1=0.25µm
poly
ndiff
Rndiff
= (11 / 3) * 2Ω/o = 7.33Ω
Cndiff
= (11* 0.25µm/*(3* 0.25µm/*0.6fF/µm2 +
(11 + 311 + 3*0.25µm/* 0.2fF/µm
= 1.24fF + 1.4fF
= 2.64fF
Note: see Table 2-4, p. 80 for parameters
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Example Problems Parasitic Calculation (4/10)
metal1
30
Corner approx.
1/2o
1=0.25µm
poly
ndiff
Rpoly
= ((3 / 2) + 1/2o + (8 / 2)) * 4Ω/o = 24Ω
Cpoly
= ( ((3* 0.25µm/*(2* 0.25µm/
((10* 0.25µm/*(2* 0.25µm/*0.09fF/µm2 +
(5 + 102 + 8+ 3+ 2*0.25µm/* 0.04fF/µm
= 0.15fF + 0.3fF
= 0.45fF
Note: see Table 2-4, p. 80 for parameters
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Example Problems Parasitic Calculation (5/10)
metal1
30
1=0.25µm
poly
ndiff
Rmetal1=0.8Ω
Cmetal1= 1.71fF
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Rndiff=7.33Ω
Cndiff= 2.64fF
May 23, 2016
Rpoly=24Ω
Cpoly= 0.45fF
69
Example Problems Parasitic Calculation (6/10)
1=0.25µm
A
What are the parasitic capacitances visible from point “A”?
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Example Problems Parasitic Calculation (7/10)
1=0.25µm
A
What are the parasitic capacitances visible from point “A”?
Cpoly
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= (6* 0.25µm/*(2* 0.25µm/*0.09fF/µm2 +
(6 + 26 + 2*0.25µm/* 0.04fF/µm
= 0.675fF + 0.16fF
= 0.84fF
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Example Problems Parasitic Calculation (8/10)
1=0.25µm
A
What are the parasitic capacitances visible from point “A”?
Cgate
= (3* 0.25µm/*(2* 0.25µm/*0.9fF/µm2
= 0.34fF
Remember: use Cg, not Cpoly for transistor gates!
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Example Problems Parasitic Calculation (9/10)
1=0.25µm
A
What are the parasitic capacitances visible from point “A”?
Coverhang = (2* 0.25µm/*(2* 0.25µm/*0.09fF/µm2 +
(2 + 22 + 2*0.25µm/* 0.04fF/µm
= 0.0225fF + 0.08fF
= 0.1fF
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Example Problems Parasitic Calculation (10/10)
1=0.25µm
A
What are the parasitic capacitances visible from point “A”?
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Latch-up



CMOS ICs have parastic silicon-controlled
rectifiers (SCRs).
When powered up, SCRs can turn on,
creating low-resistance path from power to
ground. Current can destroy chip.
Early CMOS problem. Can be solved with
proper circuit/layout structures.
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Parasitic SCR
circuit
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I-V behavior
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Parasitic Transistors



Parasitic bipolar transistors form at N/P junctions
Latchup - when parasitic transistors turn on
Preventing latchup:
 Add substrate contacts (“tub ties”) to reduce Rs, Rw
(more about this later) OR
 Use Silicon-on-Insulator
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Controlling Latchup - Substrate
Contacts



Purpose: connect well/substrate to power supply
Alternative term: tub tie (used by book)
Recommendations (source: Weste & Eshraghian)
 Conservative: 1 substrate contact for every supply
connection
 Less conservative: 1 substrate contact for every 5-10
transistors
 High-current circuits: use guard rings
Substrate
Contact
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Substrate
Contact
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Solution to latch-up
Use tub ties to connect tub to power rail. Use
enough to create low-voltage connection.
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Tub tie layout
p+
metal (VDD)
p-tub
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Coming Up:



Layout Design
Design Rules
Metal Migration
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