Document 7301309
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Design of Bluetooth
interface for low cost
embedded system.
Brett Carter
BDS(Hons)
ID: 18151515
Supervisors:
Charles Greif, Dr. Tim Ferguson.
22/05/2016
1
Overview
Reason for the project
Applications
Background
• Wireless communications
• Embedded device
System design
Functionality
Simulation and testing
Future work
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Reason for the project
There is an increasing desire to perform computing tasks
“on the move”.
Wireless access of large data stores is cheaper than
carrying all the information with you.
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Applications
Hand-held web browsing
Synchronization of Personal
organizer
Multiplayer gaming
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Background
Gameboy Advance
(GBA)
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16Mhz ARM CPU on
board
Very little Random
Access Memory
Reads and executes
code on an
expansion card
(cartridge)
Graphical User
Interface
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Background
Why GBA?
• Software tools freely available
• Inexpensive
• Color graphical interface
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Background
Bluetooth
• Transmits on the 2.4 GHz
industrial, scientific, and
medical (ISM) band
• Range of 10/100 meters
• Single chip designs
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Background
Why Bluetooth?
• Allows quick establishment and disconnection
of a link
• Inexpensive
• Low Power
• ISM band Does not require a license
• Avoids noise by frequency hopping
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System Design
Cartridge for GBA
Must fit GBA form factor
Non Volatile Memory for applications
Wireless link to download data
Control Hardware
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System Design
Crystal
Oscillator
Flash
RAM
Bluetooth
Device
16
24
UART
Serial
PROM
FPGA
CPLD
J
T
A
G
J
T
A
G
24
24
GBA Bus
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GBA Bus
24bit multiplexed address data bus
• 24bit address
• 16bit data
Asynchronous memory access
Random and sequential memory reads
Software enabled clock signal
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GBA Bus
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GBA Bus
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Bluetooth Module
Requires 12Mhz Crystal Oscillator
Handles profiles, connect/disconnect
Passes received data through UART
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FPGA controller
Xilinx Spartan XS10XL
Receives Serial data and makes it available for storage
Acts as a pseudo-memory location
De-multiplexes Address bus
Volatility means the device must be reprogrammed at
power-up or boot from a serial ROM
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FPGA controller
UART
Shift register
Serial
PROM
JTAG
Buffer
A23
D0-D15
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CPLD controller
Altera EPM3064
De-multiplexes (latches) address/data bus
Increments address for sequential access
Allows boot-up application to be flashed
• Through UART link from PC
• By Flash writer via the GBA Bus
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CPLD controller
A0-A23
Buffer
UART
Counter/Latch
From PC
Shift
register
JTAG
A0-A23
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CPLD controller
Transmission protocol for loading boot-up
application to memory through UART:
1 Word write to Address $123456
------$C1--$12--$34--$56--DataHi--DataLo------
256 Word write From Address $123456
----$D2--$12--$34--$56--Data0Hi--Data0Lo--Data1Hi--Data1Lo--…
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Flash Memory
Toshiba/Intel Strata flash
Non Volatile
65ns access time
128Mbit (8Mx16 bits)
Slow, difficult writing
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Software tools
VSIM - VHDL simulator
• Simulate firmware incrementally
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Software tools
Mentor DesignView
• Schematic design
Mentor Expedition PCB
• Routing Printed circuit board
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Software tools
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Functionality
Initially run default (boot-up) application,
or an application received in a previous
session
Establish an Ad Hoc link
• PC user transmits new application/game over
the link
• Application gets stored in Flash RAM
Data to be processed can also be transmitted
Close link and execute application
• Application remains in flash RAM after power is
removed
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Conclusion
Prototype design satisfies
specifications and is ready to be
manufactured
In house Manufacturing was not
possible due to circuit complexity.
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Future Work
Manufacture and populate PCB
• Synthesize all VHDL
Create Boot-up application/menu
Implement flow control for UART
transceiver
• Allows for higher speeds
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References
http://www.ziegler.desaign.de/GBA/g
ba.htm
http://www.bluetooth.org
http://www.bluetooth.com
http://www.gbadev.org
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