Teaching Functional Verification – Course Organization Design Automation Conference Sunday, June 9, 2002
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Transcript Teaching Functional Verification – Course Organization Design Automation Conference Sunday, June 9, 2002
Teaching Functional Verification
– Course Organization
Design Automation Conference
Sunday, June 9, 2002
Course Goals
Learn to use verification tools and experiment
on actual designs used in industry
Verisity Specman, IBM Rulebase
Cadence NC-Sim VHDL simulation framework
Learn to plan and carry out effective functional
verification of a design
Learn to work in teams to debug designs
Desired Outcome
By the end of the course the student
will
Have verified three example designs
provided by IBM
Have an understanding of why verification
is important
Have an understanding of the complexity
of verifying modern computer systems
Grading
Grade breakdown (Used at Penn State)
Midterm Exam:
20%
Final Exam:
20%
Verification Projects (~4): 45%
(3 Calc Labs + 1 ruleBase)
Homework (~3):
15%
(VHDL Background Check; e coding; rulebase)
Exams replaced with lab-oriented grading at UPitt
Final Exam was lab-based at Penn State
Prerequisites
Hardware description language
Use of modern EDA tools
VHDL or Verilog (MANDATORY)
simulation, synthesis, validation (Synopsys)
schematic capture tools (LogicWorks)
Logic design/Computer architecture
logical minimization, FSMs, component
design, pipelining, ISA design
Prerequisites - Instructors
Find a good T.A.
Tools: Licensing Information
Familiar with HDL;willing to explore tools
Interfaced Specman with Mentor Graphics
(Pitt, NC State) and Cadence tools (Penn
State)
Quick Start
Specman - CPU tutorial; ebasics slides
Rulebase – Buffer tutorial
Course Textbook/Notes
Janick’s textbook was used
Pitt and Penn State – “e based”
Covered first 3 chapters
Relied on Specman/Verification Advisor
IBM slides for rulebase
NCState – “VHDL based”
Supplemented with VHDL reference books
Course Outline – Penn State
Week 1: What is verification? (Chapt 1 of Janick's book; industry perspective)
Week 2: Behavioral VHDL - refresher and writing testbenches – HW1 (VHDL)
Week 3: Verification tools; Coverage metrics (Chap 2 of Janick’s book)
Week 4: Behind the simulation engine – event and cycle simulation
Week 5: Introduction to Specman and e language basics – (ebasics slides) – HW2 (e basics)
Week 6: Lab 1 introduction/Specman – CPU tutorial
Week 7: Verification plan – strategies/testcases/testbenches (Chap 3; VA)
Week 8: Lab 1 solution discussion + Lab 2 introduction + Exam 1
Week 9: More e language constructs
Week 10: Modeling structs;I/O blocks; data items– (VA)
Week 11: Lab 2 Solutions and Lab 3 discussion
Week 12: Modeling input relations/intervals/events – (VA)
Week 13: Lab 3 solutions + Introduction to Formal Verification + Lab 4
Week 14: Introduction to Rulebase/ Rulebase lab
Week 15: Exam review
Course Outline – Pittsburgh
Week 1: What is verification? (Chapt 1 of Janick's book; industry perspective)
Week 2: Hardware Functional Verification; review of Modelsim
Week 3: Verification tools; Coverage metrics (Chap 2 of Janick’s book)
Week 4: Behind the simulation engine – event and cycle simulation
Week 5: Introduction to Specman and e language basics – Verisity Tutorial
Week 6: Calc 1 Lab
Week 7: Verification plan – strategies/testcases/testbenches (Chap 3; VA)
Week 8: Calc 1 solution discussion + Calc 2 introduction
Week 9: More e language constructs
Week 10: Modeling structs;I/O blocks; data items– (VA)
Week 11: Calc 2 Solutions and Calc 3 discussion
Week 12: Modeling input relations/intervals/events – (VA)
Week 13: Calc 3 solutions + Introduction to Formal Verification + Lab 4
Week 14: Introduction to Rulebase/ Rulebase lab
Week 15: Rulebase lab
Course Outline – NC State
Lectures 1-2
Lecture 3
Lectures 4-6
Lectures 7-11
Lecture 12
Lecture 13
Lecture 14
Lecture 15
Lectures 16-19
Lectures 20,26
Lecture 21
Lectures 22-23
Lecture 24
Lecture 25
Lecture 27
Lecture 28
What is Verification?
Chapter 1
Verification Tools
Chapter 2
Verification Plan – Strategies/Testcases/Testbenches
Chapter 3
Architecting Testbenches
Chapter 6
Lab 1 Solution Discussion / Architecting Testbenches
Chapter 6
EXAM #1 –
Chapters 1,2,3,6
Lab 2 Overview / Stimulus and Response
Chapter 5
Review EXAM #1
Stimulus and Response
Chapter 5
Special Topic Day - Online NetSeminar on new verification technologies
Lab 2 Solution Discussion
Behavioral HDL
Chapter 4
Lab 3 Overview / Behavioral HDL
Chapter 4
Simulation Management
Chapter 7
EXAM #2 – Chapters 5,4,7 Chapter 6
Lab Day
Student Feedback
More quizzes/homework on “e” language
More time with labs especially “lab 3”
Start earlier with Specman/e
Work in groups on labs
Access to VA
Appreciate change from VHDL testbench to Specman
environment (when doing lab 1 in dual form)
Appreciate change to Rulebase from Specman
Labs were most interesting part
More time with Rulebase