Transcript 332:437 Lecture 13 FSM Asynchronous Inputs, Clocks, and Hazards

332:437 Lecture 13
FSM Asynchronous Inputs, Clocks,
and Hazards
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Asynchronous inputs
Clock distribution
Counters
State reduction
Synchronizing Sequences
Races and Hazards
One-Hot Design
Summary
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Material from An Engineering Approach to Digital Design, by
William I. Fletcher, Prentice-Hall Inc.
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Asynchronous Inputs to FlipFlops – Big Problem
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Asynchronous input changes may cause flip-flop
values to change immediately
Differing gate propagation delays may cause
machine to enter wrong state
Timing requirements for positive edge-triggered
flip-flops 1
tlow
C
D
0
1
0
thigh
tsetup thold
D must
be fixed here
D may change here
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Runt Pulse
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Logic gate inputs – pulse must have minimum
width to cause gate output to change
Very short pulses do not cause output to change,
but could cause a blip on gate output much later
after a randomly-chosen Dt
1
1
0
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Maximum Clock Frequency
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Determined by setup and hold time on flip-flops
Necessary relationships
 Tclock  thigh + tlow
tclock
C
1
0
thigh
tff
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tlow
tcomb
tsetup
Tclock  tff + tcomb + tsetup
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Clock Skew
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Very big problem in all electronics systems
Caused by unequal wire length or gate delays
D1 Q1
x
C Q1
C1
CLK
tff
C1
C2
1
0
y1
D2 Q2
C2
y2
C Q2
delay
t
td
td
1
0
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thold
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New Clock Skew Constraints
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td + thold  tff (min)
Minimum flip-flop delay
So td  tff (min) – thold
Solutions:
1. Never Gate the Clock! Violated all the time
by VLSI designers to save circuit power
2. Introduce matched delay l on clock line to C1
3. Design clock wiring so that same wire length
exists from clock source to all flip-flops (Htree)
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Example H-Tree
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Most of VLSI circuit signal propagation delay is
caused by the wiring
 Same distance from clock source to all X’s
CLK
Chip
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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Counters
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Repeat a state after some number, N, of clock
pulses
Mod N – remainder after dividing by N
If counter in state n after m clock pulses, will be
in state n after m + N, m + 2N, … pulses
States assigned as 0 to 2N – 1
Binary Up Counter – sequence 0 to 2N – 1
Binary down counter – reversed up counter
sequence
Decade up counter – 0, 1, 2, …, 10n – 1, 0, 1, 2
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Ripple Counter – 4-bit Binary
A0
1 J Q
0
0
CLK
C
1 K0
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A2
A1
1 J Q
1
1
C
1 K1
1 J Q
2
2
C
1 K
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A3
1
1
J3 Q3
C
K3
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Counter Timing Behavior
CLK
A0 0
1
0
1
0
1
0
1
0
0
1
t
1
0
0
1
1
0
A2 0
0
0
0
1
1
1
0
A3 0
0
0
0
1
t
0
0
0
0
1
t
A1 0
t
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Counter Categories
ripple (asynchronous)
binary
octal
decimal
special
synchronous ripple carry
parallel carry
 To make a counter decimal:
From count 1001 go to 0000
Right after we enter 1010 state
Q1
Q3
up
down
up/down
000
Reset
NOT USED because of gate races &
unpredictable counting results
• Considered to be a poor design
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Up/Down Control
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Change direction:
1. Use Q side to drive next clock
2. Use Q signals as counter outputs
3. Change negative edge to positive edge flipflops
Problems:
1. Very Slow
2. Varying gate & flip-flop delays can cause
malfunctions
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Better (More Reliable)
Counters
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1.
2.
3.
Synchronous
All clocks connected in parallel
Faster
Operation Mode: Whenever all least significant
bits are 1, next digit must change
0000
0001
0010
Use T flip-flops
0011
0100
…
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Parallel Carry Generation
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Counts only when both EnableP & EnableT are 1
EnableP
RCO
T0Q0
EnableT
C
CLR
/CLR
T1Q1
C
CLR
T2Q2
C
CLR
T3Q3
C
CLR
CLK
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Synchronous Counter with
Ripple Carry
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EnableP
4 Gate delays for output carry generation as
opposed to 1 gate delay
T0Q0
EnableT
C
CLR
/CLR
T1Q1
C
CLR
T2Q2
C
CLR
RCO
T3Q3
C
CLR
CLK
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Shift Registers
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Types:
1. Serial-in, serial-out
2. Serial-in, parallel-out
3. Parallel-in, parallel-out
4. Bidirectional parallel-in, parallel-out
Use a barrel shifter whenever possible:
1. Less hardware
2. Faster
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Reduction of Finite State
Machines
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Method:
 Try all possible input sequences & note
differences in output sequences
• Note non-equivalent states
x
z
Example Mealy machine: 0
1
1
0
A
0
A B
0
C
0
B D
0
B
0
C E
0
F
0
D E
0
F
0
E D
0
1
F C D/1 0
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Problems of State Partitioning
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Cannot just look for identical rows in State
Transition Table
Frequently, the machine cycles between three or
more states that are actually equivalent, but the
rows in the State Transition Table for these 3
states do not look the same
 Therefore, just looking for identical rows
causes you to miss equivalent states
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State Reduction by Method of
Partitions
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First partition – all states
P0: (ABCDEF)
 Apply X = 0 – No difference in behavior
 Apply X = 1 – If in F, output is 1, otherwise
output is 0
• Leads to second partition
P1: (ABCDE) (F)
 Apply X = 0 to ABCDE – no output difference
 Apply X = 1 to ABCDE – If in ABC, stay in
ABCDE partition, if in DE, go into another
partition (F)
• Leads to third partition
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Method of Partitions
(concluded)
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P2: (ABC) (DE) (F)
 Apply X = 0 to ABC – If in A, stay in ABC, if in
BC, go to DE
• Leads to fourth partition
P3: (A) (BC) (DE) (F)
 Apply X = 0 to BC – goes to DE
 Apply X = 1 to BC – stays in BC
 Apply X = 0 to DE – stays in DE
 Apply X = 1 to DE – goes to F
• No further partitioning possible
Also works for Moore Machines
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Synchronizing Sequences
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Input sequence that causes a Finite State
Machine to be in a specified state, regardless of
its initial state at the beginning of the sequence
Example:
X
0 1
A A B
B C B
C B B
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Example
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Ambiguity Tree finds synchronizing sequences
 Implicitly computes differences in state
ABC
behavior
0
1
0
ABC
0
1
ABC
B
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ABC
1
0
C
B
0
1
B
0
B
C
B
1
1
0
B
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C
B
1
B
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Synchronizing Sequences
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Exist for B & C but not for A
State
Shortest Synchronizing Sequence
B
1
C
10
Not all sequences are synchronizing sequences –
e.g., 00
If a Synchronizing Sequence Exists for State Si,
then it exists for all States Sj reachable from
state Si
Strongly Connected Finite State Machine
 All states reachable from every state
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Search of Ambiguity Tree
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Want to find SHORTEST synchronizing sequence
for each state, so:
 Search tree in a breadth-first manner
Labels in tree are called the ambiguity – indicate
the uncertainty about which state the machine is
in
Once you have explored the tree for a given
ambiguity
 If you encounter the same ambiguity again,
you need not search it, as you will get the
same answer you got last time you explored it
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Synchronizing Sequences
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If  Synchronizing Sequence, then for a FSM
to be strongly connected, we must have a
synchronizing sequence for all states
Must first reduce FSM to find the shortest
synchronizing sequence
Finite Memory Span: FSM has finite memory
span of length K if:
1. All input sequences  K are synchronizing
sequences
2. Each state can be reached by a
synchronizing sequence of length  K
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Example
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Reduce:
 P0: (ABCD)
 P1: (ABD) (C)
 P2: (AD) (B) (C)
 P3: (AD) (B) (C)
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A
B
C
D
0
B
B
B
B
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A
C
D/1
D
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Reduced Machine
A
B
C
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0
B
B
B
1
A
C
A/1
ABC
0
1
B
0
B
AC
1
C
0
B
1
A
Use synchronizing sequences as state
assignments: B = 00 or 10, C = 01, A = 11
Use D flip-flops
Get a shift register realization of machine
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Coded State Transition Table
State
B
C
A
B
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May be an
inexpensive
realization
State
Assignment
00
01
11
10
x
CLK
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X
0
X0/0
X0/0
X0/0
X0/0
1
01/0
11/1
11/0
01/0
D2 Q2
D1 Q1
C Q2
C Q1
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Races and Hazards
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Z-hazard – a glitch on a state machine output
Race – change of more than one Flip-Flop
required by State Transition Table
 Example: going from state 10 to 01
Non-critical race – correct operation occurs no
matter which Flip-Flop changes first
Critical race – possible to make a mistake and
end up in the wrong state when the wrong FlipFlop changes first
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Static and Dynamic Hazards
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Static Hazard – Momentary transient in output signal that
should have remained static in response to input change
 Exists whenever there are adjacent input combinations
in K-Map with same output & no map sub–code covers
both combinations
 Generally, 1
0 transition causes hazard
Dynamic Hazard – Multiple momentary transient in output
signal that should have changed only once in response to
input change
Essential Hazard -- Operational error causing transition to
improper state in response to input changes, caused by
excessive delay on feedback variable in response to input
change
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Hazard Examples
Static
Dynamic
Input
Output
1.
2.
3.
4.
Caused by circuit delays, which are randomly
distributed during chip manufacturing
Essential hazards exist only in sequential
circuits with 2+ feedbacks
Result from a combination of both delay &
design specifications
Can be controlled by adjusting the state
assignment
 Requires understanding of asynchronous
circuit design
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Static Hazards
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Theorem: A static 0 (1) hazard exists if there is a pair of
adjacent states with 0 (1) outputs and there is no 0 (1)
set that covers both
No static hazards in network if:
1.
There is a 1 (0) set that covers every adjacent input
state having an output of 1 (0)
2.
There are no 1 (0) sets containing exactly 1 pair of
complemented literals
Essential Hazard – a property of the circuit input/output
behavior
1.
No way to eliminate it
2.
There will be some combination of circuit delays will
cause a glitch, no matter how you realize the circuit
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Static Hazard Example
c
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ab
0
1
00 01
0
1
0
1
11
1
0
10
1
0
Static Hazard due to transition between 2
implicants not being covered in the Karnaugh
map
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Static Hazard Example
z
0
1
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xy
00 01 11 10
0
0 0
1
1
1 0
1
Hazard-free SOP realization
 SOP is hazard-free, here, provided that we do
not factor it
Hazard in POS
Tradeoff between simplicity of design and
hazard-free operation
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SOP and POS Realizations
x
z
x
y
z
z
x
y
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T
x
y
1
O
2
When y = 1, z = 0, x 0
1, and Gate 1 is faster
than Gate 2 in the POS realization, there is a
Hazard in the POS realization
SOP is hazard-free, here, provided that we do
not factor it
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Shift Register Implementation
of State Machines
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Possible if synchronizing sequence exists for all
states and synchronizing sequence is used as
state assignment
Example:
X
a/0
b/0
State Assignment:
X
a 1000
X
b 0100
X
c 0010
d/1
c/0
d 0001
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Realization
D1 Q1
D2 Q2
D3 Q3
D4 Q4
C Q1
C Q2
C Q3
C Q4
OUTPUT
CLOCK
INIT
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Moebius (Johnson) Counter
A shift register whose rightmost bit is inverted
and fed back into its leftmost bit
 Leads to very efficient state machine
realization
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CLOCK
INIT
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D1 Q1
D2 Q2
C Q1
C Q2
OUTPUT
State Assignment:
a 00
b 10
c 11
d 01
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One-Hot Design
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Use 1 D Flip-Flop (FF) for each state, only 1 D FF
set to 1 at any given time
Advantage: Look at appropriate D FF to see if
the machine is in the corresponding state
 Grossly simplifies output decoder
Disadvantage: In a mprocessor, could lead to
billions of FFs
 Leads to huge amounts of hardware and an
untestable machine
Use this method ONLY for relatively simple
machines
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One-Hot Design of Prior
Example
0/0
1
1/0
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0/0
2
0/0
0/0
1/0
3
1/0
4
1/0
5
1/1
0/0
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State Transition Table
X
State
1
2
3
4
5
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0
2/0
2/0
2/0
2/0
2/0
1
1/0
3/0
4/0
5/0
5/1
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State Assignment:
1 10000
2 01000
3 00100
4 00010
5 00001
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Example (continued)
Code
D1D2D3D4D5
10000
01000
00100
00010
00001
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X
0
1
State
01000/0 10000/0
1
01000/0 00100/0
2
01000/0 00010/0
3
01000/0 00001/0
4
01000/0 00001/1
5
Read out equations from Coded Table:
D1 = XQ1
Z = XQ5
D2 = X
D3 = XQ2
D4 = XQ3
D5 = XQ4 + XQ5 = X (Q4 + Q5)
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Logic Gate Realization
x
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
C Q1
C Q2
C Q3
C Q4
C Q5
CLOCK
INIT
x
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Summary
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Asynchronous inputs
Clock distribution
Counters
State reduction
Synchronizing Sequences
Races and Hazards
One-Hot Design
Bushnell: Digital Systems
Design Lecture 13
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