Transcript MICE Tracker Readout Increased Data Readout Rate VLSB Development 16 AFE II t boards 8 Visible Light Photon Counter (VLPC) cassettes 4 cryostats.

MICE Tracker Readout
Increased Data Readout Rate
VLSB Development
16 AFE II t boards
8 Visible Light Photon Counter (VLPC) cassettes
4 cryostats
AFE-IIt Terms
• AFE-IIt: Second version of D0 Analog Front End boards which read out times
(in addition to charges)
• TriP-t: Trigger with Pipeline including time data
– Provides discriminator output
– Provides time and charge amplitudes of earlier events stored in pipeline
• FPGA: Field Programmable Gate Arrays
– Analog FPGAs (AFPGAs) control operation of Trip-t chips and ADCs.
– Digital FPGAs receive discriminator bitmap and send bitmap to AFPGAs.
• VLSB: VME LVDS Serdes Buffer banks where processed data are stored.
– VME: Versa Module Europa bus system
– LVDS: Low Voltage Differential Signaling
– Serdes: Serializer/deserializer transceiver that converts parallel data to serial data
and vice-versa.
MICE Requirements for Tracker Readout
• Data Rate: MICE has established goal of reading out 600 muons
every 1 ms spill.
– D0 tracker readout optimized for TeVatron beam.
– For MICE, current microcoding allows ~225 muons/ms.
• Data Readout: MICE tracker data will be read out to VLSB banks.
– D0 data read out to digital boards and SVX sequencers.
Data Rate
• What needs to be done:
– Firmware providing bitmap to the AFPGA to implement data
rate scheme (Senerath’s talk reports progress.).
– Firmware modification which accepts bitmap from DFPGA.
– Verification of digitization with input signals.
– Further modifications to make data readout compatible with
ISIS beam.
Data Readout
• What’s been done recently:
– Wrote firmware which has VLSB store data from multiple triggers before
readout.
– Verified that VLSB hardware is fine and that firmware modifications are
needed for MICE operation.
• What needs to be done:
– Work with D0 VLSB experts to fix/modify VLSB firmware.
– Test this AFE-IIt readout to VLSB with LED/cryostat/VLPC system.
List of Details
• Synchronicity with ISIS beam:
– Make sure that TriP-t chip is active when there’s ISIS beam
– TriP-t active time controlled by AFPGA signals
– Efficiency depends on uniformity of ISIS beam period
• Can we use only one (~ 18 ns) clock cycle for channels below threshold?
– Now use 2 cycles for channels below threshold and 6 cycles for channels above threshold.
– Current capability of ~ 490 muons per 1 ms spill increased to ~ 660 muons per spill if
implemented.
– Not straightforward, but worth considering
• Use ChipScope to check digitization code.
– ChipScope uses FPGA block RAMs as logic analyzers to monitor signals.
• Decide on data format for AFPGAs with no data.
– Suitable for Senerath’s firmware
– Suitable for Malcolm’s data unpacking
– Need to work with Kwame for resolution of possible needed data padding
Longer Term Considerations
• Test that ADCs and TriP-t chips will work
– Understand specifications
– Develop simulations
– Run TriP-t standalone and/or AFE-IIt platform
tests.
• Understand tracker readout dead time
Anticipated Schedule
•
Now: AFE-IIt boards reserved for MICE
• We have 8 AFE-IIt boards (4 LH and 4 RH).
• Paul Rubinov, supervisor of the AFE-IIt testing, told me
“MICE gets boards when MICE needs boards.”
•
Late November, early December: Firmware coding done
•
Late November: Firmware testing with input signals and AFE-IIt boards.
•
Late 2006, early 2007: Test AFE-IIt readout to VLSB with cryostat/LED/VLPCs.