Transcript OptiFlex Asad Chaudhry Guthrey Coy Brandonn Gorman Review of Project Objectives/Goals • Develop a “self-aware” fiber optic mesh that is conscious of its current state.

OptiFlex
Asad Chaudhry
Guthrey Coy
Brandonn Gorman
Review of Project Objectives/Goals
• Develop a “self-aware” fiber optic mesh that
is conscious of its current state (temperature,
shape, strain, etc.) by using Bragg graded fiber
• Display the data on a monitor
FBG
Block Diagram
Optical
Processing I/O
Laser
Analog
Mux’s
Photodiodes
Single mode
couplers
500MHz
Oscillator
A/D
Converter
FPGA
FBG cable
LCD Display
VGA
Monitor
Functional Decomposition
Level 1
Level 0
Module 1
Outputs
Functionality
FPGA
4 switches: (Calibrate, Temperature,
Pressure, Shape), 12 bit Binary Data from
ADC, Busy
LCD, Red LED's, VGA, ADC interfacing, Analog
Mux Select Lines
Indicate what is being read
Module 2
Optical Array
Inputs
Laser (centered at 1518nm)
Outputs
Functionality
36x unique voltage measurements
Detects changes in Shape, Stress,
Temperature
Module 3
External A/D
Inputs
36x photodiodes, WR, CR, RD, ADC Select
Lines (A0, A1, A2), Analog Input(AIN0, AIN1,
AIN2, AIN3, AIN4, AIN5, AIN6, AIN7), Mux
Select Lines (A, B, C), 500MHz Clk
Outputs
12 bit Binary Data, Busy
Functionality
Convert the voltage measurements from the
photodiodes to readable data
Inputs
Module 1.1
Processor
Functionality
Switches/button, 12 bit Binary Data from ADC,
Busy, 50MHz Clk
WR, CR, RD, ADC Select Lines (A0, A1, A2), Mux
Select Lines (A, B, C), LCD_data[7..0], LCD_RW,
LCD_RS, LCD_E, LCD_ON, LCD_BLON, Output to
Red LED's[17..0], DRAM_CLK,
SRAM_ADDR[17..0], SRAM_CE_N,
SRAM_DQ[15..0], SRAM_LB_N, SRAM_OE_N,
SRAM_UB_N, SRAM_WE_N
Process and output all data. Handle all
conversations with the ADC/Analog Mux’s.
Module 2.1
Fiber Array
Inputs
36x Fused Fiber Couplers
Outputs
36x Reflected Data Signals from Gratings
Functionality
Detect Environmental Changes
Module 2.2
Photo Diode Array
Inputs
36x Fused Fiber Couplers
Outputs
36x Voltage Signals
Functionality
Convert IR Intensity signal to Voltage
Inputs
Outputs
Functional Decomposition
Level 2
Module 1.1.1
Calibration
Module 1.1.5
LCD Display
Inputs
1 Switch, 1 push button, data matrix
Inputs
Data Array
Outputs
Calibration data (Array)
Outputs
Visual Display of Sensory Data
Functionality
Standardized data array for an initial condition
Functionality
Display Information about a single Fiber
Module 1.1.2
Temperature
Module 1.1.6
VGA Display
Inputs
1 Switch, calibration data, data matrix
Inputs
Data Array
Outputs
Data array
Outputs
VGA Output
Functionality
process A/D data into meaningful Temperature
data
Functionality
Display Information about the Fiber Grid
Module 1.1.3
Pressure
Module 1.1.7
Red LED Display
Inputs
1 Switch, calibration data, data matrix
Inputs
Data Array
Outputs
Data array
Outputs
Functionality
process A/D data into meaningful Pressure
data
Red LED’s
Provide qualitative analysis of data from a
single fiber.
Module 1.1.4
Shape
Inputs
1 Switch, calibration data, data matrix
Outputs
Data array
Functionality
process A/D data into meaningful shape data
Functionality
D
N
G
D
N
G
2.2uf
.1uF
Cap
Cap
D
N
G
D
N
G
Converter
A/D
S
C
D
R
DATA
.1uF
Vref
Cap
AINI
R
W
AGND
DGND,
BUSY
CLK
Clock
R
FPGA
S
D
Vdd
C
R
W
BUSY
Vdd
D
N
Mux
Com
G
Data
C
C
Vcc
B
B
A
A
INH
D
N
G
Out
D
N
G
Out
*
*
PhotoDiode
External A/D Converter Circuit
Components/Budget
Part
Vendor
Part #
Lead Time Quantity
Price
Total
Running Total
Micron
Optics
OS1100
2-3 Days
36
$39
$1,404
$1,404
FIS
SDW13550122UC 3-5 Days
70
$19.95
$1,396.50
$2,800.50
Optical Components
FBG
1550nm 1x2 Coupler 50/50
Split
Photo Diode
Fermionics FD300W
3-5 Days
36
$40.00
$1,440.00
Photo Diode (Alternate)
DigiKey Via OED-PPD11085GLumex Opto B
3-5 Days
36
$37.90
$1,364.40
$4,164.90
Tunable Laser
HP
1
Provided Provided
$4,164.90
1
Provided Provided
$0
HP81678F
Electrical Components
Altera Cyclone II DE2
Altera
Analog Digital Converter
Texas Inst
ADS7852
4
$6
$24
$24
MUX
Texas Inst
SN74LV4051A-Q1
10
$0.62
$6.20
$30.20
External Clock
Raltron
CO6
Schedule
Division of Labor
Task
Asad
Guthrey
Optics assembly
x
FPGA Interfacing
PCB Design and
Assembly
Brandonn
x
x
Calibration Module
x
LCD Display Module
x
VGA Display Module
x
x
Shape Module
x
x
Pressure Module
x
Temperature Module
x
Documentation
x
x
x
Testing
x
x
x
x
x
FPGA Block Diagram
Completed Code
#include "system.h"
#include "sys/alt_irq.h"
#include "altera_avalon_pio_regs.h"
#include "altera_avalon_timer_regs.h"
#include <stdlib.h>
#include <unistd.h> //e.g. //usleep(5000000); is 5 seconds
#include <stdio.h>
#include <io.h>
#include <altera_avalon_uart_regs.h>
#include "priv/alt_busy_sleep.h"
#include "altera_avalon_lcd_16207_regs.h"
void lcd_init( void) {
usleep(15000); /* Wait for more than 15 ms before init */
/* Set function code four times -- 8-bit, 2 line, 5x7 mode */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x38);
usleep(4100); /* Wait for more than 4.1 ms */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x38);
usleep(100); /* Wait for more than 100 us */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x38);
usleep(5000); /* Wait for more than 100 us */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x38);
usleep(100); /* Wait for more than 100 us */
#define LCD_WR_COMMAND_REG 0
#define LCD_RD_STATUS_REG 1
#define LCD_WR_DATA_REG 2
#define LCD_RD_DATA_REG 3
/* Set Display to OFF*/
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x08);
usleep(100);
void lcd_disp ( char k[], int i, char g[], int u){
int j;
/* Set Display to ON */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x0C);
usleep(100);
/* Set the Cursor to the home position */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x02);
usleep(2000);
/* Set Entry Mode -- Cursor increment, display doesn't shift */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x06);
usleep(100);
/* Display clear */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x01);
usleep(2000);
/* Set the Cursor to the home position */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x02);
usleep(2000);
for(j = 0; j < i; j++){
IOWR(LCD_0_BASE, LCD_WR_DATA_REG,k[j]);
usleep(100);
}
/* Set the cursor to the second line
*
* */
for(j = 0; j < u; j++){
IOWR(LCD_0_BASE, LCD_WR_DATA_REG,g[j]);
usleep(100);
}
}
/* Display clear */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x01);
usleep(2000);
}
char convert_int_to_char(int x) {
if (x >= 0 && x <= 9)
return (x + '0');
else {
convert_int_to_char(x/10);
return (x%10 + '0');
}
}
Completed Code
alt_u32 clear_lcd(void) {
/* Set the Cursor to the home position */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x02);
usleep(2000);
/* Display clear */
IOWR(LCD_0_BASE, LCD_WR_COMMAND_REG, 0x01);
usleep(2000);
return(0);
}
void led_disp(char led_val){
IOWR_ALTERA_AVALON_PIO_DATA(RED_LEDS_BASE, (led_val & 0xFF));
}
void adc_handler(int adc_data[]){
int count = 0,i,j;
for(i=0; i < 3; i++){
IOWR_ALTERA_AVALON_PIO_DATA(ADC_SEL1_BASE,i);
for(j=0; j < 7; j++){
IOWR_ALTERA_AVALON_PIO_DATA(MUX_SEL1_BASE,j);
IOWR_ALTERA_AVALON_PIO_DATA(CS1_BASE,0);
IOWR_ALTERA_AVALON_PIO_DATA(WR1_BASE,0);
//might need usleep() here to wait for BUSY to go low
while(BUSY1_BASE != 1)
usleep(100);
IOWR_ALTERA_AVALON_PIO_DATA(WR1_BASE,1);
IOWR_ALTERA_AVALON_PIO_DATA(RD1_BASE,0);
adc_data[count] = DATA1_BASE;
IOWR_ALTERA_AVALON_PIO_DATA(CS1_BASE,1);
IOWR_ALTERA_AVALON_PIO_DATA(RD1_BASE,1);
count++;
}
}
}
Planned Deliverables
Milestone 1
•
•
Working ADC
Completed interfacing code
Milestone 2
•
•
•
Working single fiber sensor
Temperature and Pressure module completed
Mesh completely assembled
Any Questions?