Methods to Differentiate Mil/Aero Solutions Using FPGAs Dan Gardner Final MAPLD Presentation Agenda Why FPGA technology is important Technology to consider for FPGA EDA software Why you.
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Methods to Differentiate Mil/Aero Solutions Using FPGAs Dan Gardner Final MAPLD Presentation Agenda Why FPGA technology is important Technology to consider for FPGA EDA software Why you need these for Mil/Aero FPGA Gardner 2 MAPLD 2005/P145 FPGAs overtake ASICs in Mil/Aero Segment Military/Aerospace Market 2002 2003 2004 2005 2006 2007 2008 $ 3,751 $3,783 $4,357 $4,360 $4,295 $4,648 $5,160 ASIC $176 $188 $206 $219 $220 $212 $202 FPGA/PLD $158 $190 $222 $238 $253 $301 $381 ASIC Growth 7% 9% 7% 0% -4% -5% FPGA/PLD Growth 20% 17% 7% 6% 19% 27% Total Semiconductor Source: Gartner Dataquest Gardner 3 MAPLD 2005/P145 FPGAs overtake ASICs in Mil/Aero Segment $450 30% $381 $400 $350 $250 $200 20% $301 $300 $176 $158 $188 $190 $222 $206 $238 $219 $253 $220 25% 15% $212 $202 10% 5% $150 $100 0% $50 -5% $- -10% 2002 2003 ASIC 2004 2005 FPGA/PLD 2006 ASIC Growth 2007 2008 FPGA/PLD Source: Gartner Dataquest Gardner 4 MAPLD 2005/P145 Requirements for FPGA software in Mil/Aero Cost effective delivery of mission performance — Initial Creation Cost and speed of design — — — — Complete Verification — Predictable time to market at fixed cost Fast iterations Timing and system closure Commercial FPGA often skips many verification steps Some Mil/Aero applications have additional considerations Maintenance of Project Cost of life cycle maintainability of design Support of standard platforms Support Mil-preferred devices, documentation and flows Gardner 5 MAPLD 2005/P145 FPGA Technologies are Very Competitive Many FPGA selections available — High-performance choices — High-volume choices — Altera Stratix II/GX Xilinx Virtex-4 Actel ProASIC3/3E Altera Cyclone II Lattice LatticeEC/ECP Xilinx Spartan-3/3E Radiation Tolerant choices Actel RTAX-S Xilinx QPro Gardner 6 MAPLD 2005/P145 Widespread Use in Mil/Aero Complex applications require latest FPGA technologies Software defined radio — Platform-based computing — Reconfigurable computing — DSP algorithms in hardware co-processors — On the other end of the spectrum are the radiation tolerant devices Low volumes fit FPGAs better than ASICs in many cases Gardner 7 MAPLD 2005/P145 Technologies to Consider All technologies listed below are required to build a complete methodology and will be covered This presentation will essentially focus on the unique requirements of Mil/Aero FPGA applications: — — — — — — Rule checker with platform-independent coding styles Design management RTL + physical synthesis I/O design with integration path to PCB System-level design Verification — Electronic System-Level (ESL) Overview Assertion based (CDC to validate SEU protection) Coverage Driven Clock domain crossing (CDC) Embedded systems Gardner 8 MAPLD 2005/P145 Rule Checkers Static Design Checking for VHDL/Verilog RTL Encapsulate knowledge: – – Use Early and Often: — — — — Expect built-in checks from standard sources – Reuse Methodology Manual – FPGA vendor recommendations Must allow quick customization for your own checks Perform checking interactively or in batch Understand the causes of violations Easily interact, organize, & track violations Interactively trace & fix violations Share knowledge: — — — Share checks with the team/company Allow any designer to apply accumulated knowledge Export results for reporting Gardner 9 MAPLD 2005/P145 Put a Senior Designer on Everyone’s Shoulder Do not re-learn from the same mistakes over and over again Code Browser indicates errors & warnings Code lines highlighted Hover help for each violation Step through errors Trace to graphics Show rule/rule help Rerun analysis Gardner 10 MAPLD 2005/P145 Designing in Teams Progressive development, validation, implementation — — Supports team standards — Designers work in parallel, from RTL placed gates Top-down & bottom-up methodology freedom Code, graphical appearance, tool preferences, design flows Manages multiple versions of the design Long design existence requires reproducible flows Multiple contracts on single, long-term projects require comprehensive, customized design management tools Synthesize FPGA Vendor P&R Gardner 11 MAPLD 2005/P145 Version Management Simulate Process Automation Design Visualization for Design Reviews & Reuse Strict documentation and traceability rules dominate Mil/Aero design Effective implementation of IP reuse — Minimize additional design for reuse time — Automate processes and policies to design IP Minimize design time to include IP Automate analysis of IP for fast implementation Gardner 12 MAPLD 2005/P145 Design and IP Reuse Flows FIRM macro blocks enhance design productivity at physical implementation level Achieve predictable results for FPGA fabric family Seamless porting between like-family FPGA devices Helps in easy verification Gardner 13 MAPLD 2005/P145 Platform FPGA Technology vs. Pushbutton FPGA Design Flow Major technology changes in platform FPGA — More gates per part — Specialized embedded technology — Specialized interconnect — High-speed device effects Emerging design challenges — Design debug process is unreliable for complex designs — Harder to bring quality product to market quickly — Harder to manage flows: — Design reuse & IP integration Harder to predict development costs Gardner 14 MAPLD 2005/P145 Control for Complex Requirements Fully integrated RTL synthesis and physical synthesis capabilities — Enhances RTL Synthesis — Before Physical Synthesis Takes physical considerations into account Linking physical data with logic synthesis RTL to placed gates Improves productivity by enhancing design analysis Cross selection between RTL code, schematic, physical and timing views — Physically aware IP and design reuse Improves time to design completion — Improves performance by interactively optimizing the placed design Gardner 15 After Physical Synthesis MAPLD 2005/P145 Advanced FPGA Methodologies Physical Awareness Fulfills Key Technology Needs Placement reuse/ECO — — Divide and conquer approach — — Gardner Add new functionality safely Add/change RTL code w/ minimum placement impact Meet challenging design requirements quickly Isolate & optimize tricky portions of circuitry 16 MAPLD 2005/P145 System Design Trends Average FPGAs on a single PCB One 32% Two 16% Average pins of largest FPGA Three 5% 250 to 499 pins 25% Four 500 to 749 pins 13% 750 to 999 pins 7% 4% Five or more 5% None 38% 1000 to 1499 pins 19% Almost half of all PCBs with FPGAs have multiple FPGAs per PCB 100 to 249 pins 27% 1500 pins or more Less than 100 2% pins 7% Many FPGAs now over 500 pins 2004 EDA Study Gardner 17 MAPLD 2005/P145 Isolated Flows with Manual Integration FPGA & PCB teams typically don’t communicate well — All information entered and synchronized manually — Package, speed-grade, pin assignments Information must stay consistent in three locations FPGA, PCB schematic, PCB layout Gardner 18 MAPLD 2005/P145 FPGA PCB Designer Issues Best location to meet Board constraints Best location to meet FPGA constraints The FPGA must work on the board and the overall system must work — Each design engineer has his own constraints to achieve May be in conflict/unsupportive of partner designer Need to converge on a trade-off acceptable to both parties Gardner 19 MAPLD 2005/P145 Design Languages & Tasks Requirements Text / UML Architectural Analysis tools aren’t … Algorithm Exploration C/C++ Untimed SystemC Architecture Analysis Transaction Level SystemC …adopted by RTL Designers Verification VHDL Verilog RTL Design Task Language Gardner 20 MAPLD 2005/P145 Design Languages & Tasks Requirements Text / UML Algorithm Exploration C/C++ Untimed SystemC Architecture Analysis HVL’s Extend & Accelerate the RTL Design Process Transaction Level SystemC Verification System Verilog Assertions PSL/SVA VHDL Verilog RTL Design Task Language Gardner 21 MAPLD 2005/P145 Design Languages & Tasks Requirements Text / UML Algorithm Exploration C/C++ Untimed SystemC Architecture Analysis …and enable RTL Designers to cross the chasm to system level design Transaction Level SystemC Verification System Verilog Assertions PSL/SVA VHDL Verilog RTL Design Task Language Gardner 22 MAPLD 2005/P145 C Synthesis Typical end user: hardware designer Developing compute intensive designs — Have existing C functional models — Typical Applications Wireless, satellite communications; video/image processing — Automatic frequency control (AFC), clock tracking — Viterbi, turbo decoder, Reed-Solomon — FFT, DCT, FIR filters — Gardner 23 MAPLD 2005/P145 What C Synthesis Delivers Untimed C++ synthesis Technology independent source focused on true functional intent — Connects system to hardware design domain — Micro-architecture “what if” analysis — Interface “what if” analysis — SystemC compatible — No proprietary extensions — Automated RTL creation Algorithm and data path analysis Faster verification Gardner 24 MAPLD 2005/P145 Why SystemVerilog for Design? Encapsulation allows designers to model at more abstract levels Scalability makes incremental design changes simpler Code re-usability increases design efficiency Easier to model accurate, synthesizable models of any size designs Not only system-level designers need SystemVerilog Both Synthesis and Simulation benefit from SystemVerilog Gardner 25 MAPLD 2005/P145 Summary of SystemVerilog Design SystemVerilog increases productivity for both synthesis and simulation — Can use existing VHDL and Verilog modules mixed with SystemVerilog Interface features: — Ability to encapsulate functionality as well as connectivity — Ability to replace a group of names by a single name New concise and powerful implicit port connection features speed design entry and provide early type checking Allows designers to take advantage of new abstract architectural models Allows designers to insert assertions directly into RTL code Gardner 26 MAPLD 2005/P145 Abstraction Drives Design Productivity Source Implementation Simulation 20x (2 days!!) Algorithmic C++ Functional 10,000x (1 min) Untimed TLM SystemC Structural 1,000x Timed TLM SystemC Transaction 100x Cycle Accurate SystemC Cycle 10x 2x (2 weeks) RTL 1x (7 days) 1x (5 weeks) RTL Gardner 27 MAPLD 2005/P145 Automatic Generation of Verification Infrastructure Original C++ Testbench Facilitates the Verification of the synthesized design The original C++ testbench can be reused to verify the design Transactor — — Original C++ Algorithm RTL or Cycle Accurate SystemC, VHDL or Verilog RTL Transactors convert function calls to pin-level signal activity Pushbutton verification solution includes Makefiles and Simulation scripts Transactor Comparator Golden results DUT results Gardner 28 MAPLD 2005/P145 Exhaustive Algorithm Verification With Automated Real Time Prototypes — ? Quickly produce RTL code from algorithmic specifications Regardless of the quality of the architecture Run RTL synthesis and P&R with integrated tool flows Validate the functional correctness of the algorithm on FPGA prototyping boards — Architecture optimization can be pursued in parallel Algorithms Catapult C Synthesis C Code Constraints RTL Code Constraints Precision RTL Synthesis Netlist Constraints FPGA Vendor P&R Prototyping Gardner 29 MAPLD 2005/P145 Functional Flaws Driving Need for Re-Spin IC/ASIC Designs Requiring Re-Spins by Type of Flaw 71% 75% Logic/Functional Clocking Tuning Analog Circuit Fast Path Yield/Reliability Delays/Glitches Slow Path Mixed-Signal Interface Power Consumption IR Drops Market Study 2002 Market Study 2004 Firmware Other 0% 20% 40% 60% 80% Percent of Designs Requiring Two or More Silicon Spins …the Problem is Getting Worse Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission Gardner 30 MAPLD 2005/P145 100% Methodology Explosion Targeting Verification Assertion-based verification Functional coverage Constrained-random testing Coverage-driven verification Dynamic-formal verification Transaction-level verification Model checking And more . . . Gardner 31 MAPLD 2005/P145 SystemVerilog for Verification SystemVerilog is a complete Verification Language — — Can be used with VHDL Stimulus generation capabilities — Functional coverage modeling — Measure the verification quality and test effectiveness Dynamic reactivity with constrained-random stimulus generation Assertion-Based Verification — Dynamically configurable constrained-random value generation Ability to generate constrained-random stimulus sequences Ability to randomly select control paths (test scenario selection, etc.) Property specification Assertion & coverage monitoring High-level modeling (programming) capabilities Efficiently and effectively model the operational environment Develop reusable verification environments Gardner 32 MAPLD 2005/P145 Assertion-Based Verification Assertions Enable Higher Quality Designs Assertions provide observability for higher complexity designs — ABV makes assertions a key element, ensuring that design properties are not violated Assertions describe (un)desired behavior Assertions dramatically shorten debug and repair time Reference Model Assertions stay on during block, chip and system-level tests — Finds bugs you weren’t looking for Gardner Bus Monitor 33 Assertion Checkers Bus Monitor Assertion Checkers MAPLD 2005/P145 Coverage-Driven Verification Verification is effectively metric-less — Few designers know if their strategy is adequate or efficient — Sign-off criteria are ad hoc and vary by company — Code coverage is not a functional verification metric Gardner 34 MAPLD 2005/P145 Expect Widespread Use of Coverage-Driven Verification PSL and SystemVerilog provide coverage constructs Simulators integrating functional coverage to improve performance and debug New test strategies require functional coverage — Random and constrained random tests need coverage to determine what they tested Gardner 35 MAPLD 2005/P145 Clock-Domain Crossings Incorrect handling of Clock-Domain Crossing (CDC) signals is the 2nd major cause of re-spins Traditional verification techniques do not work for CDC signals CDC problems are subtle, will occur in hardware, and are complex to debug Assertion Synthesis automates CDC verification, significantly reducing the risk of CDC-related silicon re-spins Gardner 36 MAPLD 2005/P145 Common CDC Myths Adding correct synchronizers on all paths is all that is needed — I can detect protocol violations by sweeping clocks in my simulation — Even if implemented perfectly, protocol errors and reconvergence error will still exist Is very reliant on luck, and will only detect a small subset of errors I use special synchronizers that add a random delay, so I am covered for reconvergence — This only works for paths that contain synchronizers, and lacks the automation and coverage necessary to significantly reduce risk. A complete CDC solution MUST verify the structural correctness, transfer protocols, and deep sequential reconvergence, otherwise bugs WILL be missed Gardner 37 MAPLD 2005/P145 Platform FPGAs Need a Complete Flow Software Platform Studio IDE Platform Exp Stacks ASAP Code|Lab BSP Microtec Nucleus Hardware Seamless ISS Modelsim XRAY SW-HW OnChip Debug OPB GPIO OPB OPB Arbiter Arbiter PCB, Signal Integrity Tools Gardner Precision Inventra Synthesis 16550 UART EMC EMC Cntrl Cntrl OPB OPB <> <> PLB PLB PLB PLB Arbiter Arbiter 32KB 32KB BRAM BRAM BRAM BRAM Cntrl Cntrl 38 Chipscope ISE Tools JTAG JTAG PPC PPC 405 405 MAPLD 2005/P145 HW/SW Co-verification: Faster Iteration Loop Without Co-verification With Co-verification HDL Entry HDL Entry Synthesis HDL Compile Seamless FPGA Co-Verification Implementation Evaluation Board Download Bitstream Into FPGA Gardner 39 Supports: Edit/Compile/Verify Eliminates: Edit/Synthesize/ Implement/Download/Verify Promotes: Superior Visibility and Control MAPLD 2005/P145 Processors Require SW Tools Embedded software to cover it all Executable and UML Suite Translatable UML solution Dev Tools generates embedded code Prototyping Eclipse-powered Middleware complete, integrated RTOS development tool suite Prototype whole software application Source code, royalty-free RTOS & middleware Gardner 40 MAPLD 2005/P145 Support for Processor-based FPGAs RTOS support for both Xilinx MicroBlaze and PowerPC architectures and Altera NIOS, NIOS II and ARM architectures Target software debugger and build environment Support for Xilinx Spartan3, Virtex II Pro, and Virtex-4 and Altera Cyclone II and Stratix II Embedded software suite for FPGA system design must include complete tool offerings and target software platform, including high-level modeling with xtUML and advanced target software debugging environment. Gardner 41 MAPLD 2005/P145 Summary With engineers from software, hardware and system disciplines all converging on FPGAs, it is important to focus on the methods that can help differentiate your solution from others. It is necessary to use all the basic verification and design tools, but there are new technologies emerging that can better address the unique requirements of Mil/Aero applications. Gardner 42 MAPLD 2005/P145