Transcript ECE 545 Digital System Design with VHDL Course web page: ECE web page  Courses  Course web pages  ECE 545 http://ece.gmu.edu/coursewebpages/ECE/ECE545/F09/

ECE 545
Digital System Design with VHDL
Course web page:
ECE web page  Courses  Course web pages
 ECE 545
http://ece.gmu.edu/coursewebpages/ECE/ECE545/F09/
Kris Gaj
Research and teaching interests:
• reconfigurable computing
• computer arithmetic
• cryptography
• network security
Contact:
The Engineering Building, room 3225
[email protected]
Office hours: Monday, Tuesday, Wednesday
6:00-7:00 PM
ECE 545
Part of:
MS in Computer Engineering
Required course in two concentration areas:
Digital Systems Design
Microprocessor and Embedded Systems
Elective course in the remaining concentration areas
MS in Electrical Engineering
Elective
Courses
Design level
Digital System Computer
Design with VHDL Arithmetic
VLSI Design VLSI Test
for ASICs
Concepts
algorithmic
register-transfer
ECE
545
ECE
645
ECE
681
gate
ECE
586
transistor
layout
devices
ECE
680
ECE
682
Digital
Integrated
Circuits
Physical
VLSI Design
Semiconductor
ECE 584
ECE684
Device Fundamentals
MOS Device
Electronics
DIGITAL SYSTEMS DESIGN
Concentration advisors: Kris Gaj, Ken Hintz
1. ECE 545 Digital System Design with VHDL
– K. Gaj, project, FPGA design with VHDL,
Aldec/Synplicity/Xilinx
2. ECE 645 Computer Arithmetic
– K. Gaj, project, FPGA design with VHDL or Verilog,
Aldec/Synplicity/Xilinx
3. ECE 681 VLSI Design for ASICs
– N. Klimavicz, project/lab, back-end ASIC design with
Synopsys tools
4. ECE 586 Digital Integrated Circuits
– D. Ioannou, R. Mulpuri
5. ECE 682 VLSI Test Concepts
– T. Storey
Grading Scheme
• Homework
- 10%
• Project
- 40%
• Midterm Exam- 20%
• Final Exam
- 30%
Midterm exam 1
 2 hours 30 minutes
 in class
 design-oriented
 open-books, open-notes
 practice exams will be available on the web
Tentative date:
Thursday, October 21st
Final exam
 2 hours 45 minutes
 in class
 design-oriented
 open-books, open-notes
 practice exams will be available on the web
Date:
Wednesday, December 16, 7:30-10:15pm
Hash Function
arbitrary length
m
message
h
It is computationally
infeasible to find such
m and m’ that
h(m)=h(m’)
h(m)
fixed length
hash
function
hash value
Main Application: Digital Signature
Signature
HANDWRITTEN
DIGITAL
A6E3891F2939E38C745B
25289896CA345BEF5349
245CBA653448E349EA47
Main Goals:
• unique identification
• proof of agreement to the contents
of the document
Typical Digital Signature Scheme
Alice
Bob
Message
Message
Signature
Signature
Hash
function
Hash
function
Hash value 1
Hash value
yes
no
Hash value 2
Public key
cipher
Alice’s private key
Public key
cipher
Alice’s public key
Handwritten and Digital Signatures
Common Features
Handwritten signature
Digital signature
1. Unique
2. Impossible to be forged
3. Impossible to be denied by the author
4. Easy to verify by an independent judge
5. Easy to generate
Handwritten and Digital Signatures
Differences
Handwritten signature
Digital signature
6. Associated physically 6. Can be stored and
with the document
transmitted
independently
of the document
7. Almost identical
7. Function of the
for all documents
document
8. Usually at the last
8. Covers the entire
page
document
Cryptographic Standards
So how the cryptographic standards
have been created so far?
NSA
National Security Agency
(also known as “No Such Agency”
or “Never Say Anything”)
Created in 1952 by president Truman
Goals:
• designing strong ciphers (to protect U.S. communications)
• breaking ciphers (to listen to non-U.S. communications)
Budget and number of employees kept secret
Largest employer of mathematicians in the world
Larger purchaser of computer hardware
NSA-developed Cryptographic Standards
Block Ciphers
2005
1999
1977
DES – Data Encryption Standard
Triple DES
1993 1995
Hash Functions
2003
SHA-1–Secure Hash Algorithm
SHA-2
SHA-0
1970
1980
1990
2000
2010
time
Cryptographic Standard Contests
IX.1997
X.2000
AES
15 block ciphers  1 winner
NESSIE
I.2000
XII.2002
CRYPTREC
XI.2004
V.2008
34 stream ciphers  4 SW+4 HW winners eSTREAM
X.2007
51 hash functions  1 winner
XII.2012
SHA-3
96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12
time
Criteria used to evaluate cryptographic
transformations
Security
Hardware
Efficiency
Software
Efficiency
Flexibility
Software or hardware?
HARDWARE
SOFTWARE
security of data
during transmission
speed
random key
generation
low cost
flexibility
(new cryptoalgorithms,
protection against new attacks)
access control
to keys
resistance to
side-channel attacks
tamper resistance
Primary efficiency indicators
Hardware
Software
Speed
Memory
Speed
Area
Power
consumption
Efficiency parameters
Latency
Mi
Encryption/
decryption
Ci
Throughput = Speed
Mi+2
Mi+1
Mi
Time to
encrypt/decrypt Encryption/
a single block
decryption
of data
Ci+2
Ci+1
Ci
Number of bits
encrypted/decrypted
in a unit of time
Block_size · Number_of_blocks_processed_simultaneously
Throughput =
Latency
Advanced Encryption Standard (AES) Contest
1997-2001
June 1998
15 Candidates
Round 1
from USA, Canada, Belgium,
France, Germany, Norway, UK, Israel,
Korea, Japan, Australia, Costa Rica
Security
Software efficiency
Flexibility
August 1999
5 final candidates
Mars, RC6, Rijndael, Serpent, Twofish
October 2000
1 winner: Rijndael
Belgium
Round 2
Security
Hardware efficiency
Speed of the final AES candidates in Xilinx FPGAs
Speed [Mbit/s]
K.Gaj, P. Chodowiec, AES3, April, 2000
500
450
400
350
300
250
200
150
100
50
0
Serpent Rijndael Twofish RC6
Mars
Survey filled by 167 participants of
the Third AES Conference, April 2000
# votes
100
90
80
70
60
50
40
30
20
10
0
Rijndael Serpent Twofish
RC6
Mars
Results of the NSA group
ASICs
Speed [Mbit/s]
AES3, April, 2000
700
NSA
ASIC
606
600
500
414
GMU
FPGA
431
400
300
202
177
200
105
143
103
100
57
61
0
Rijndael Serpent Twofish RC6
Mars
Efficiency in software: NIST-specified platform
200 MHz Pentium Pro, Borland C++
Speed [Mbits/s]
128-bit key
192-bit key
256-bit key
30
25
20
15
10
5
0
Rijndael
RC6
Twofish Mars Serpent
NIST Report: Security
AES Final Report, October 2000
Security
High
Serpent
MARS
Twofish
Adequate
Rijndael
RC6
Simple
Complex
Complexity
eSTREAM Stream Cipher Comparison
• Part of the GMU Fall 2006 & Fall 2007 graduate courses
ECE 545 Introduction to VHDL
• Individual 6-week project
• 4 students working independently on each eSTREAM cipher
• best code for each algorithm selected at the end
of the semester
• selected designs verified and revised in order to assure
• correct functionality
• standard interface & control
• possibly uniform design & coding style
Comparison of 4 Focus Hardware-Oriented Stream Ciphers
FPGA: Xilinx Spartan 3 family
Throughput
[Mbit/s]
Best
T64
12000
10000
Trivium
8000
T32
6000
4000
T16
G16
2000
Phelix
Grain
G1
0
0
Mickey-128
200
400
AES
600
Worst
800
1000 1200 1400
Area
[CLB slices]
Comparison of 8 Final Candidates Sorted by
Minimum Area and Maximum Throughput/Area
Candidate
Area
(slices)
Candidate
Throughput/Area
(Mbps/slices)
Grain v1
44
Trivium (x64)
39.26
Grain 128
50
Grain 128 (x32)
7.97
Trivium
50
Grain v1 (x16)
5.98
DECIM v2
80
Trivium
4.80
DECIM 128
89
F-FCSR-16
4.53
MICKEY 2.0
115
Grain v1
4.45
MICKEY 128 2.0
176
Grain 128
3.92
Moustique
278
F-FCSR-H v2
3.23
F-FCSR-H v2
342
MICKEY 2.0
2.03
Trivium (x64)
344
MICKEY 128 2.0
1.27
Grain v1 (x16)
348
Moustique
0.81
F-FCSR-16
473
DECIM v2
0.58
Grain 128 (x32)
534
DECIM 128
0.49
Pomaranch
648
Edon80
0.10
Edon80
1284
Pomaranch
0.08
Conclusions from the Comparison
of the eSTREAM Candidates in
Hardware
Very large differences among 8 leading candidates:
~30 x in terms of area (Grain v1 vs. Edon80)
~500 x in terms of the throughput to area ratio
(Trivium (x64) vs. Pomaranch)
Your Project
• 14 SHA-3 candidates left in the contest
• Given:
 specification of the function
 reference implementation in C
 interface
 testbench (without test vectors)
• Generate:
 synthesizable code in VHDL
 results for Xilinx FPGAs
 optimized versions of the code
 results for multiple families of FPGAs
All Projects - Organization
• Projects divided into phases
• Deliverables for each phase submitted through Blackboard
at selected checkpoints and evaluated by the instructor
and/or TA
• Feedback provided to students on a best effort basis
• Final report and codes submitted using Blackboard
at the end of the semester
Honor Code Rules
• All students are expected to write and debug
their codes individually
• Students are encouraged to help and support
each other in all problems related to the
- operation of the CAD tools,
- basic understanding of the problem.
Course Objectives
• At the end of this course you should be able to:
• Code in VHDL for synthesis
• Decompose a digital system into a controller (FSM) and datapath,
and code accordingly
• Write VHDL testbenches
• Synthesize and implement digital systems on FPGAs
• Understand behavioral, non-synthesizable VHDL and its role in
modern design
• Effectively code digital systems for cryptography, signal
processing, and microprocessor applications
• This knowledge will come about through homework, exams,
and an extensive project
• The project in particular will help you know VHDL and the FPGA
design flow from beginning to end
35
Hands-On Sessions
Wednesday, September 9, 2009
The Engineering Building, Room 3204
Group 1: 4:30-7:10pm
Group 2: 7:20-10:00pm