Transcript CS 140 Lecture 17 System Designs III Professor CK Cheng CSE Dept. UC San Diego.

CS 140 Lecture 17
System Designs III
Professor CK Cheng
CSE Dept.
UC San Diego
1
System Designs
1.
2.
3.
4.
Methodology
Hierarchy
Flow and Process
Technology-Oriented
Construction
2
Digital Designs vs Computer
Architectures
• Instruction Set (H.Chapter 6, CSE141)
– Bottleneck: Silicon Area, Power
• Data Path (H.Chapter 7.1-7.3)
• Control Subsystem (H.Chapter 7.1-7.3)
• Memory Management (Chapter 8, CSE141)
– Bottleneck: IO, Memory Latency
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Design Process
• Program of Hardware Description
• List of Data Operations
• Data Path
– Read control signals. Output conditions
• Control Subsystem
– Read conditions. Output control signals
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Example: Multiplication
Arithmetic
Z=X x Y
• M<=0
• For i=n-1 to 0
– If Yi=1, M<=M+X 2i
• Z<=M
Input X, Y
Output Z
Variable M, i
• M<=0
• For i=n-1 to 0
– If Yn-1=1, M<=M+X
– Shift Y left by one bit
– If i != 0, shift M left by
one bit
• Z<=M
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Implementation: Example
{ Input X<15:0>, Y<15:0> type bit-vector,
start type boolean;
Local-Object A<15:0>, B<15:0> ,M<31:0>,
i<4:0> type bit-vector;
Output Z<31:0> type bit-vector,
done type boolean;
S0: If start’ goto S0;
S1: A <= X || B <= Y || i<=0 || M<=0 || done <= 0;
S2: If B15 = 0 goto S4 || i<=i+1;
S3: M <= M+A;
S4: if i>= 16, goto S6
S5: M<=Shift(M,L,1) || B<=Shift(B,L,1) || goto S2;
S6: Z<= M || done<= 1|| goto S0;
}
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Implementation: Example
{ Input X<15:0>, Y<15:0> type bit-vector,
start type boolean;
Local-Object A<15:0>, B<15:0> ,M<31:0>,
i<4:0> type bit-vector;
Output Z<31:0> type bit-vector,
done type boolean;
S0: If start’ goto S0;
S1: A <= X || B <= Y || i<=0 || M<=0 || done <= 0;
S2: If B15 = 0 goto S4 || i<=i+1;
S3: M <= M+A;
S4: if i>= 16, goto S6
S5: M<=Shift(M,L,1) || B<=Shift(B,L,1) || goto S2;
S6: Z<= M || done<= 1|| goto S0;
}
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Z=XY
16
X
Data
Y 16 Subsystem
B15 i4
start
32
Z
C0-7
Control
Subsystem
done
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Data Path Subsystem
operation
A  Load (X)
A <= X
B  Load (Y)
B <=Y
M Clear(M)
M<=0
i Clear(i)
i<=0
i  INC(i)
i<=i+ 1
M Add(M,A)
M<=M+A
M<=Shift(M,L,1) M  SHL(M)
B<=Shift(B,L,1) B  SHL(B)
Wires
Z<=M
control
C0
C2
C4
C6
C7
C5
C1
C3
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Data Path Subsystem
C1
A
X
16
SHL
LD
Add
M
Z
CLR LD
C0
C4 C5
Y
i
B
LD SHL
C2 C3
B<15>
CLR Inc
C6 C7
i<4>
i<4>
B<15>
start
Control
Unit
C0-7
done
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Control Subsystem
C1
A
X
16
LD
SHL
Add
M
Z
CLR LD
C0
C4 C5
i
B
Y
LD SHL
B<15>
CLR Inc
i<4>
C6 C7
C2 C3
C0
C1
C2
C3
C4
C5
C6
C7
done
S0
0
0
0
0
0
0
0
0
1
S1
1
0
1
0
1
0
1
0
0
S2
0
0
0
0
0
0
0
1
0
S3
0
0
0
0
0
1
0
0
0
S4
0
0
0
0
0
0
0
0
0
S5
0
1
0
1
0
0
0
0
0
S6
0
0
0
0
0
0
0
0
1
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Control Subsystem
start’
S6
S0
start
S1
S5
S2
i<4>’
i<4>
B<15>’
B<15>
S3
S4
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Exercises:
1. Implement the control
subsystem with one-hot state
machine design.
2. Try to reduce the latency of the
whole system.
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