Transcript Advanced Avionics Systems for Dependable Computing in Future Space Exploration Leon Alkalai, Savio Chau, Ann Tai Center for Integrated Space Microsystems Jet Propulsion Laboratory California.

Advanced Avionics Systems for
Dependable Computing in Future Space Exploration
Leon Alkalai, Savio Chau, Ann Tai
Center for Integrated Space Microsystems
Jet Propulsion Laboratory
California Institute of Technology
GOMAC – 2002
March 12th, 2002
/JPL/Publications/2002/GOAMC/gomac-presentation.ppt
[email protected]
URL: http://cism.jpl.nasa.gov
Tel. 818 354-5988
Fax. 818 393 5013
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L. Alkalai, March 12,2002
Potential Customers:
Mars 09 Smart Lander/Rover Mission
Conduct Significant
Science*
• Sub-surface drilling
• In-situ soil/rock analysis
• Atmospheric measurements
SURFACE MOBILITY
Demonstrate Next-Generation
Lander/Rover Capabilities
GUIDED ENTRY
• Global access
• latitude range
• surface elevation
• rugged terrain
Approach
• Strong, multi-
• Accurate/safe landing
• “Go-to” mobility
• Extended mission operations
disciplinary team
• NASA centers
• Industry
• Universities
• Early pre-project
with extensive
technology program
HAZARD DETECTION/AVOIDANCE
*No “strawman” payload yet defined, examples
of possible experiments listed
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ROBUST TOUCHDOWN SYSTEM
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L. Alkalai, March 12,2002
Potential Customers:
Solar System Exploration (circa 2008)
Europa Orbiter/Lander
Cassini/Huygens
Titan Explorer
Comet Nucleus
Sample Return
GalileoEuropa
Exploring Organic Rich Environments:
• Extreme Radiation Environments
• Extreme Temperature Environments
• Long Duration missions
• Long latency of communications
– highly autonomous operations
– miniaturization of systems
– design for high survivability, fault-tolerance, and
high availability
Pluto/Kuiper Express
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L. Alkalai, March 12,2002
Potential Customers:
Astrophysics (2009)
Laser Interferometry Space Antenna (LISA)
Space Interferometry Mission (SIM)
Space based Interferometry
• High precision metrology
• Pico-meter laser interferometry
– Highly miniaturized electronics
– High performance computing
– Micro-Newton Thrusters
– Disturbance reduction control
– High Performance inertial sensors
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L. Alkalai, March 12,2002
Dependable Computing in Previous
Deep Space Missions
• Typical Dual-String Designs for Spacecraft
Point-to-Point Architecture
Bus-Based Architecture
Mass
Memory
Mass
Memory
Mass
Memory
Mass
Memory
Flight
Computer
Flight
Computer
Flight
Computer
Flight
Computer
I/O
Interface
I/O
Interface
Bus
Interface
Bus
Interface
Telecom
Telecom
Telecom
Telecom
Attitude
and GN&C
Attitude
and GN&C
Attitude
and GN&C
Attitude
and GN&C
Power
Power
Power
Power
Science
Instruments
Science
Instruments
Science
Instruments
Science
Instruments
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L. Alkalai, March 12,2002
Dependable Computing in
New Generation of Deep Space Mission
• Characteristics of New Generation of Deep Space Missions:
– Many missions focus on autonomous landers, rovers, sample return, etc.
– Missions requirements are much more demanding:
•
•
•
•
•
•
•
•
Precision autonomous navigation, including Aero-Braking and Aero-Capture
Precision landing
Entry, Descent and Landing Hazard avoidance
Much higher processing requirements
Distributed processing
Much higher interface bandwidth requirements
Autonomous operation
High speed fault detection and recovery
– The systems are physically smaller with higher functional density
– Shrinking mission operation budget means smaller mission operations team
• Must rely on on-board autonomous fault tolerance
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L. Alkalai, March 12,2002
High-Performance Fault-Tolerant
Bus Architecture Research at JPL
• Requirements for Distributed Processing, High Interface Bandwidth, and High
Speed Fault Recovery Necessitate the Development of a High Speed Fault
Tolerant Bus Architecture
• Commercial-Off-The-Shelf (COTS) Bus Standards Are Highly Desirable
Because of Cost, Availability, and Performance Benefits.
• Two COTS Bus Standards Were Selected for the initial X2000 design:
– the IEEE 1394 and I2C
• However, These COTS Buses Are Not Designed for the Highly Reliable
Applications Such As Deep Space Missions. Therefore, the Focus of the
Research is How to Achieve Highly Reliable Avionics Bus Architecture Using
COTS Bus Standards
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L. Alkalai, March 12,2002
Baseline X2000 COTS Bus Architecture
NVM
NonNVM
Volatile
Memory
1 to N
Computers
N < 64
SFC
SFC
Flight
Computer
global memory
SIO
SIO
(SIO)
I/O
(SIO)
Interface
Micro
Controller
(NVM)
PCI
NVM
NVM
NonNVM
Volatile
Memory
NVM
NVM
NonNVM
Volatile
Memory
PCI
1394 Bus - 100Mbps
(Symbolic, topology not shown)
Power
Control
(Bus)
I2C Bus - 100kbps
1394 Bus - 100Mbps
Power
Control
(Bus)
I2C Bus - 100kbps
PCI
Telecom
Micro
Controller
(ACS)
Micro
Controller
(Power)
IMU
IMU
Frame
Grabber
SFG
RS422
Star
Camera
SSA
Sun
Sensor
ISI
Interface
Temp.
Sensor
RS422
Sun
Sensor
IMU
Power
Control
PCS
Battery
Control
BCS
Switch
Module
(loads)
Switch
Module
(loads)
Power Regulation & Control, Valve & Pyro Drive,
Analog Telemetry Sensors
Attitude Determination
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Single Master, Subsystem I2C Bus
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Multi-Layer Fault Tolerance Methodology
for COTS-Based Bus Architecture
• Mutually Assisted Fault
Isolation & Recovery
• Different topology
•Protocol Enhancements
•Fail-Silence Protocol
•Heartbeat & Polling
•Isochronous Ack
•Link Layer Fail-Silence
•Watchdog timers
•Redundant bus sets
•Diverse bus topology
System Level Redundancy (Layer 4)
Design Diversity
(Layer 3)
Mutually Assisted Recovery
(Layer 3: Design Diversity)
Enhanced
Fault
Tolerance
(Layer 2)
Enhanced
Fault
Tolerance
(Layer 2)
Enhanced
Fault
Tolerance
(Layer 2)
Enhanced
Fault
Tolerance
(Layer 2)
1394 Bus
Native
Fault
Tolerance
(Layer 1)
I2C Bus
Native
Fault
Tolerance
(Layer 1)
1394 Bus
Native
Fault
Tolerance
(Layer 1)
I2C Bus
Native
Fault
Tolerance
(Layer 1)
•Header & Data CRC
•Ack Packets w. Error Code
•Ack Packet Parity
•Response Packet Error Code
•Timeout Conditions
•Port Enable/Disable
Presentation for Paper “A Design-Diversity
/JPL/Publications/2002/GOAMC/gomac-presentation.ppt
•Ack bit
Based Fault-Tolerant COTS9Avionics Bus Network. CL#01-1161
L. Alkalai, March 12,2002
A Framework for the Design of Highly Survivable
Avionics Systems using COTS
Design
Analysis
Fault propagation path
System Level Redundancy (Layer 4)
Design Diversity
(Layer 3)
Design Diversity
(Layer 3)
Enhanced
Fault
Tolerance
(Layer 2)
Enhanced
Fault
Tolerance
(Layer 2)
Enhanced
Fault
Tolerance
(Layer 2)
Enhanced
Fault
Tolerance
(Layer 2)
COTS # 1
Native Fault
Tolerance
(Layer 1)
COTS # 2
Native Fault
Tolerance
(Layer 1)
COTS # 1
Native Fault
Tolerance
(Layer 1)
COTS #2
Native Fault
Tolerance
(Layer 1)
Leakage = Q4
System Level
Redundancy
(Level 4)
Leakage = Q3
Design
Diversity
(Level 3)
Leakage = Q2
Enhanced
Fault Tolerance
(Level 2)
Leakage = Q1
COTS Native
Fault Tolerance
(Level 1)
Fault Propagation Model
of Multi-Layer Design
L. Alkalai, A. T. Tai, “Long-Life Deep-Space Applications,” Computer, IEEE, Vol. 31, No. 4, IEEE Computer Society, April 1998, pp. 37-38.
S. Chau, L. Alkalai, and A. T. Tai, "The Analysis of Multi-Level Fault-Tolerance Methodology for Applying COTS in Mission-Critical
Systems," in Proceedings of the IEEE Workshop on Application-Specific Software Engineering and Technology (ASSET'2000), Dallas, TX,
March 2000.
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X2000 Fault Containment Regions
NVM
NonNVM
Volatile
Memory
1 to N
Computers
N < 64
SFC
SFC
Flight
Computer
global memory
SIO
SIO
(SIO)
I/O
(SIO)
Interface
Micro
Controller
(NVM)
PCI
NVM
NVM
NonNVM
Volatile
Memory
NVM
NVM
NonNVM
Volatile
Memory
PCI
1394 Bus - 100Mbps (Symbolic, topology not shown)
Power
Control
(Bus)
I2C Bus - 100kbps
1394 Bus - 100Mbps
Power
Control
(Bus)
I2C Bus - 100kbps
PCI
Telecom
Micro
Controller
(ACS)
IMU
IMU
Micro
Controller
(Power)
Frame
Grabber
SFG
RS422
Star
Camera
SSA
Sun
Sensor
ISI
Interface
Temp.
Sensor
RS422
Sun
Sensor
IMU
Power
Control
PCS
Battery
Control
BCS
Switch
Module
(loads)
Switch
Module
(loads)
Power Regulation & Control, Valve & Pyro Drive,
Analog Telemetry Sensors
Attitude Determination
/JPL/Publications/2002/GOAMC/gomac-presentation.ppt
Single Master, Subsystem I2C Bus
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A Highly Reliable Distributed Network
Architecture for Future Missions
•
•
•
Support distributed computing
Rich set of redundant interconnections
Multi-layer fault tolerance design
to ensure fault containment
1394 Bus 1 Backup Connections
#1
Bus 1 Root
Bus 2 Leaf
1394 Bus 2 Backup Connections
#2
Bus 1 Branch
Bus 2 Leaf
#3
#4
Bus 1 Branch
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Root
1394 Bus 1
I2C Bus 1
I2C Bus 2
1394 Bus 2
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Branch
#5
#6
1394 Bus 2 Backup Connections
#7
#8
1394 Bus 1 Backup Connections
L. Alkalai, S. Chau, A.Tai, J.B. Burt, "The Design of a Fault-Tolerant COTS-Based Bus Architecture," Proceedings of 1999 Pacific Rim International Symposium On
Dependable Computing (Prdc'99), Hong Kong, China December 16-17, 1999. Also, IEEE Trans. Reliability, Vol. 48, December 1999, pp. 351-359.
A. Tai, S. Chau, L. Alkalai, "COTS-Based Fault Tolerance in Deep Space: Qualitative and Quantitative Analyses of A Bus Network Architecture" will appear in
proceedings of HASE 99: Fourth IEEE International Symposium on High Assurance System Engineering, Washington DC Metropolitan Area, November 17-19, 1999.
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Realization of Multi-Level
Fault Protection Methodology
Cable IEEE 1394 has a tree topology
1394 Bus 1 Backup Connections
Enhanced Fault Tolerance
(An Example)
1394 Bus 2 Backup Connections
#2
#1
Bus 1 Root
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
#3
#4
Bus 1 Branch
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Root
1394 Bus 1
Design Diversity
I2C Bus 1
I2C Bus 2
1394 Bus 2
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Branch
#5
#6
1394 Bus 2 Backup Connections
#7
#8
1394 Bus 1 Backup Connections
System Level Redundancy with Diverse Topology
Presentation for Paper “A Design-Diversity
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Based Fault-Tolerant COTS13Avionics Bus Network. CL#01-1161
L. Alkalai, March 12,2002
X2000 Fault Protection Strategy
1394 Bus 1 Backup Connections
1394 Bus 2 Backup Connections
#2
#1
Bus 1 Root
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
#3
#4
Bus 1 Branch
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Root
1394 Bus 1
I2C Bus 1
I2C Bus 2
1394 Bus 2
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Branch
#5
#6
1394 Bus 2 Backup Connections
#7
#8
1394 Bus 1 Backup Connections
Presentation for Paper “A Design-Diversity
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Based Fault-Tolerant COTS14Avionics Bus Network. CL#01-1161
L. Alkalai, March 12,2002
X2000 Fault Protection Strategy
Possible Recovery Initiator
•IEEE 1394 Root
•IEEE 1394 IRM
•IEEE 1394 Bus Manager
1394 Bus 1 Backup Connections
•I2C Prime Master
1394 Bus 2 Backup Connections
#2
#1
Bus 1 Root
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
#3
#4
Bus 1 Branch
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Root
1394 Bus 1
I2C Bus 1
Interrogate
I2C Bus 2
1394 Bus 2
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Branch
#5
#6
1394 Bus 2 Backup Connections
#7
#8
1394 Bus 1 Backup Connections
Presentation for Paper “A Design-Diversity
/JPL/Publications/2002/GOAMC/gomac-presentation.ppt
Based Fault-Tolerant COTS15Avionics Bus Network. CL#01-1161
L. Alkalai, March 12,2002
X2000 Fault Protection Strategy
1394 Bus 1 Backup Connections
#3 Failed
1394 Bus 2 Backup Connections
#2
#1
Bus 1 Root
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
#3
#4
Bus 1 Branch
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Root
1394 Bus 1
I2C Bus 1
Reconfigure
I2C Bus 2
1394 Bus 2
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Branch
#5
#6
1394 Bus 2 Backup Connections
#7
#8
1394 Bus 1 Backup Connections
Presentation for Paper “A Design-Diversity
/JPL/Publications/2002/GOAMC/gomac-presentation.ppt
Based Fault-Tolerant COTS16Avionics Bus Network. CL#01-1161
L. Alkalai, March 12,2002
X2000 Fault Protection Strategy
1394 Bus 1 Backup Connections
#1
Bus 1 Root
Bus 2 Leaf
1394 Bus 2 Backup Connections
#2
Bus 1 Branch
Bus 2 Leaf
#3
#4
Bus 1 Branch
Bus 2 Leaf
Bus 1 Branch
Bus 2 Leaf
Bus 1 Branch
Bus 2 Branch
Bus 1 Leaf
Bus 2 Root
1394 Bus 1
I2C Bus 1
I2C Bus 2
1394 Bus 2
Bus 1 Leaf
Bus 2 Branch
Bus 1 Leaf
Bus 2 Branch
#5
#6
1394 Bus 2 Backup Connections
#7
#8
1394 Bus 1 Backup Connections
Next fault recovery needs repair
before bus switching if this node fails
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I2C Bus Fault Protection: Fail Silence
Flight
Computer
Flight
Computer
Microcontroller
I2C Bus
Sensor
Presentation for Paper “A Design-Diversity
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Sensor
Actuator
Based Fault-Tolerant COTS18Avionics Bus Network. CL#01-1161
L. Alkalai, March 12,2002
I2C Bus Fault Protection: Fail Silence
Flight
Computer
Timeout
Flight
Computer
Timeout
Microcontroller
Timeout
Babbling
I2C Bus
Sensor
Presentation for Paper “A Design-Diversity
/JPL/Publications/2002/GOAMC/gomac-presentation.ppt
Sensor
Actuator
Based Fault-Tolerant COTS19Avionics Bus Network. CL#01-1161
L. Alkalai, March 12,2002
I2C Bus Fault Protection: Fail Silence
Flight
Computer
Unmute
Flight
Computer
Microcontroller
Babbling
Unmute
Unmute
I2C Bus
Unmute
Sensor
Presentation for Paper “A Design-Diversity
/JPL/Publications/2002/GOAMC/gomac-presentation.ppt
Sensor
Actuator
Based Fault-Tolerant COTS20Avionics Bus Network. CL#01-1161
L. Alkalai, March 12,2002
Architecture Testbed Configuration
PCI Bus
analyzer
Built-In Power Supply
Built-In Power Supply
cPCI bus (6U chassis)
cPCI bus (6U chassis)
cPCI bus (6U chassis)
Empty Slot
Empty Slot
Empty Slot
Empty
1553BSlot
BC
1394a I/F (Saderta)
PPC 750 (Synergy)
Hard Drive
1394a I/F (Saderta)
Empty Slot
Empty Slot
Empty Slot
PPC 750 (Synergy)
PMC
Empty
1553B Slot
BC
1394a I/F (Saderta)
1394a I/F (Saderta)
PPC 750 (Synergy)
Empty Slot
Empty Slot
Empty Slot
Hard Drive
PPC 750 (Synergy)
PMC
Empty
1553B Slot
BC
1394a I/F (Saderta)
1394a I/F (Saderta)
PPC 750 (Synergy)
Hard Drive
PPC 750 (Synergy)
PMC
Built-In Power Supply
Terminal
Server
SUN Ultra 10
Workstation
cPCI bus (6U chassis)
cPCI bus (6U chassis)
Built-In Power Supply
Built-In Power Supply
Empty Slot
Empty Slot
Empty Slot
1553B Slot
BC
Empty
1394a I/F (Saderta)
1394a I/F (Saderta)
PPC 750 (Synergy)
Hard Drive
PPC 750 (Synergy)
Empty Slot
Empty Slot
Empty Slot
Empty
1553B Slot
BC
1394a I/F (Saderta)
1394a I/F (Saderta)
PPC 750 (Synergy)
PPC 750 (Synergy)
Hard Drive
1553 Bus
Analyzer
Pentium III
w/1394a
analyzer
(Saderta)
Legends
COTS
COTS Support Equipment
JPL In-House Product
Future Expansion
/JPL/Publications/2002/GOAMC/gomac-presentation.ppt
IEEE 1394
I2C
Pentium III
w/1394a
analyzer
(Saderta)
Ethernet
SUN Ultra 10
Workstation
SUN E3500
Workstation
(35 GB HD)
RS232
SCSI
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Example of Fault Injection in IEEE 1394 Bus
Fault Injected in the Gap Count Register in the IEEE 1394 Bus
(A)
Before Fault Injection
(B)
After Fault Injection
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Distributed Flight Computer Testbed
Power PC 750 Processors
IEEE 1394 BUS
I2c bus
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Guarded Software Upgrade
•
Motivation:
–
Flight software for long life deep space missions have to be upgraded
periodically to correct design bugs or due to change of mission phases
– Unprotected software upgrades have previously caused
severe and costly damage to space missions and critical
applications
•
Objectives:
–
–
•
Update flight software without System Reboot
Fall back to previous version of the software if failures occur during
the upgrade
Approach:
–
–
Use the old version of the software to “guard” the new version during
the transition
Turn over the control to the new software only when the right level of
confidence is reached
A. Tai, K. S. Tso, L. Alkalai, S. N. Chau, and W. H. Sanders, "On low-cost error containment
and recovery methods for guarded software upgrading," in Proceedings of the 20th International
Conference on Distributed Computing Systems (ICDCS 2000), Taipei, Taiwan, April 2000, pp.
548-555.
A. T. Tai, K. S. Tso, L. Alkalai, S. Chau, and W. H. Sanders, "On the effectiveness of a messagedriven confidence-driven protocol for guarded software upgrading,'' in Proceedings of the 4th
IEEE International Computer Performance and Dependability Symposium (IPDS 2000),
Schaumburg, IL, March 2000.
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Direction of Dependable Computing Researches for
Future Flight Missions
• Characteristics of Future Deep Space Missions:
– Future Space Exploration Missions are ambitious:
•
•
•
•
•
•
•
Precision navigation control for spacecraft aerobraking and aerocapture
Precision entry-descent-landing with hazard avoidance
Highly autonomous operations
Long-duration missions in extreme environments
Miniaturized systems for sample returns, ascent vehicles, mobile units, etc.
Distributed surface science - network science - constellations of spacecraft
Formation flying (e.g., interferometry missions)
– These missions require a new look at high performance dependable computing
• Distributed processing among multiple spacecraft, and within a spacecraft
• High performance computing and power efficient computing that supports long-life,
high availability of systems
• Autonomous, on-board fault-detection, isolation and repair
• Fault adaptation
• A framework for using COTS for the design of future, highly reliable systems
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References

“COTS-Based Fault Tolerance in Deep Space: Qualitative and Quantitative
Analyses of a Bus Network Architecture,” in Proceedings of the 4th IEEE
International Symposium on High Assurance Systems Engineering, Washington
D.C., Nov 1999

“Design of a fault-tolerant COTS-based bus architecture, ” IEEE Trans. Reliability, vol.
48, pp. 351-359, Dec. 1999

“The design of a fault-tolerant COTS-based bus architecture,” Pacific Rim
International Symposium on Dependable Computing, Hong Kong, China, Dec.
1999

"The Implementation of a COTS Based Fault Tolerant Avionics Bus Architecture", in the
Proceedings of the Aerospace 2000 Conference, Big Sky, Montana, Mar. 2000

"COTS-based fault tolerance in deep space: A case study on IEEE 1394 application,"
International Journal of Reliability, Quality and Safety Engineering, vol. 9, June 2002.

“A design-diversity based fault-tolerant COTS avionics bus network,” in Proceedings of
the Pacific Rim International Symposium of Dependable Computing (PRDC 2001), Seoul,
Korea, Dec. 2001.
Note: Some of these references can be found in http://www.ia-tech.com/obm/
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References

"On the effectiveness of a message-driven confidence-driven protocol for guarded
software upgrading," Performance Evaluation, vol. 44, pp. 211-236, Apr. 2001.

"Low-cost error containment and recovery for onboard guarded software upgrading
and beyond," IEEE Trans. Computers, vol. 51, Feb. 2002.

“Low-cost flexible software fault tolerance for distributed computing,” in Proceedings
of the 12th International Symposium on Software Reliability Engineering (ISSRE
2001), Hong Kong, China, pp.148-157, Nov. 2001.

"Synergistic coordination between software and hardware fault tolerance techniques,"
in Proceedings of the International Conference on Dependable Systems and Networks
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L. Alkalai, March 12,2002