Transcript A Large Swing, 40-Gb/s SiGe BiCMOS Driver with Adjustable Pre-Emphasis for Data Transmission over 75W Coaxial Cable Ricardo A.

A Large Swing, 40-Gb/s SiGe BiCMOS Driver
with Adjustable Pre-Emphasis for
Data Transmission over 75W Coaxial Cable
Ricardo A. Aroca & Sorin P. Voinigescu
Edward S. Rogers, Sr. Dept. of Electrical & Comp. Eng.,
University of Toronto, Toronto, ON M5S 3G4, Canada
Outline
Motivation
Driver Specifications
Driver Architecture and Design
Measurements
Transmission Experiment
Conclusions
2
Motivation
Transport 40-Gb/s over existing coaxial cable infrastructure
TX/RX
IC
Belden 1694A
Transceiver IC must be low-cost, highly integrated, and capable
of equalizing up to 50dB of channel losses
3
Transceiver Architecture
Transmit
serializer
and
40-G PLL
40-GHz
clock
Line
driver
40 Gb/s @
1 – 1.8V
FFE
40 Gb/s
@ 5V
DFE
40-GHz
clock
Timing
Recovery
• Focus on the TX, RX in development
• TX requires amplitude control and pre-emphasis control
• Place as much equalization into the TX to ease the RX specs
4
40-Gb/s, 75W Driver Specifications
Parameter
Specification
Input DC level
1 - 1.8V
Min Input Amplitude
200mVpp
Output Swing:
driving 75W
driving 50W
Gain:
1 – 5Vpp per side
0.8 – 4Vpp per side
CMOS
> 28dB
> 26dB
Bandwidth:
> 20GHz
> 25GHz
S11, S22
< -10dB up to 40GHz
Duty Cycle
30 - 70%
Pre-Emphasis
0 - 400%
PDC
~3W
5
Production Technology
Jazz HX 0.2mm SiGe BiCMOS
0.18mm n-MOSFET
NMOS
fMAX = 75GHz
fT = 50GHz
JpkfT = 0.3mA/mm
HV-HBT, BVceo=3.5V
HV-HBT
fMAX = 100GHz
fT = 75GHz
JpkfT = 2.5mA/mm2
6
Distributed Architecture Design
75W
75W Microstrip T-Line Sections
8V
8V
INP
INN
75W
1
Pre-Driver
OUTP
5V
2
3
4
5
6
7
75W
8V
OUTN
8V
AMP
75W
DCC
Amp & PreEmphasis
Itail CNTRL
• IOUT = 5Vpp/(75W//75W) = 133mA  19mA/section
• Must fully switch the DA  predriver: 1.5Vpp, 40mA
• Gain of predriver = 1.5/0.2 = 18dB, 3dB/stage  6 stages
• Distributed pre-emphasis is implemented for the first time
• Amplitude control is implemented in both the DA and predriver
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DA Section Schematic
~5V
T-line section
T-line compensation
~5V
fT=75GHz
fMAX=100GHz
HV-HBT
IOFF
C
C
IMAIN
R
R
VPRE
VPRE
IPRE
RC-HPF
0.18mm
& Digital
n-MOSFETs
HBT fT=160GHz,
fT=50GHz,fMAX
fMAX=160GHz
=75GHz
8
DA Section Schematic
~5V
T-line section
T-line compensation
~5V
IOFF
C
C
IMAIN
R
IT
R
VPRE
IT=IMAIN+IPRE
VPRE
IPRE
• IT is variable, for amplitude control at different pre-emphasis settings
• IOFF adjusts to ensure current through HV-HBT is constant
9
Driver Microphotograph
1.2mm
Predriver
Distributed Amplifier
2.5mm
10
S-parameter Measurements vs.
Simulations: 10dB of Amplitude Control
22GHz
10dB
11
S-Parameter Measurements vs.
Simulations: 25dB of Pre-Emphasis Control
25dB
12
40-Gb/s Eyes @ 25oC and 125oC
25oC
3Vpp
1Vpp
125oC
• Input: 200mVpp, 4x(231-1 PRBS)
• 2ps RMS jitter (1khits)
1.9Vpp
• ~11ps rise/fall times
13
40-Gb/s Pre-Emphasis @ 25oC and 125oC
25oC
2Vpp
1Vpp
125oC
• Input: 200mVpp, 4x(231-1 PRBS)
• 200-400% pre-emphasis
1.3Vpp
14
Maximum Output Amplitude @ 38Gb/s
3.6Vpp per side in a 50W load, 10.5ps rise time,
2.2ps RMS jitter (1.17khits)
15
40-Gb/s Driver Performance in 50W
Parameter
Target
Measured
Input DC level
1 - 1.8V
1 - 1.8V
Min Input Amplitude
200mVpp
200mVpp
Output Swing:
Gain:
driving 75W
1 – 5Vpp per side
driving 50W*
0.8 – 4Vpp per side
driving 75W
> 28dB
driving 50W*
> 26dB
Bandwidth
0.8 - 3.6Vpp per side
36dB
> 20GHz
> 25GHz
22GHz
S11, S22 (up to 40GHz)
< -10dB
< -10dB
Duty Cycle
30 - 70%
35 – 65%
Pre-Emphasis
0 - 400%
0 - 400%
~3W
3.6W
PDC
16
40-Gb/s, 50W Driver Comparison
Parameter
fT / fMAX (GHz)
GaAs [1]
InP [3]
SiGe [2]
This Work
50 / 75
HV-HBT: 75 / 100
MOS:
100 / 200
150 / 200
120 / 160
LD*
LD
LD
LD
1.7 - 3
1 - 5.65
3.4
0.8 - 3.6
16
30
-
36
-
45
-
22
30 – 70
-
-
35 – 65
PDC (W)
2.8
3
<3
3.6
Pre-Emphasis
no
no
no
0 - 400%
Topology
Swing (per side)
Gain (dB)
Bandwidth (GHz)
Duty Cycle (%)
*LD – Lumped predriver followed by a distributed amplifier
*[ ] – Reference numbers refer to those cited in the paper
17
Transmission Experiment over 10m, 30m
and 40m of Belden Coaxial Cable
INPUT TO CHANNEL
BIAS
K-SMA-BNC
RSH
4x231-1 PRBS
Source
T
T
RSH
BIAS
10m,30m,
40m coax
AFTER CHANNEL
To Remote Sampling Head (RSH)
18
Equalized Channel Response
CHANNEL
INPUT TO CHANNEL
AFTER CHANNEL
Range of all possible
equalized channel
responses
19
10-Gb/s over 40m Coax
-24dB
50mVpp
No Pre-emphasis
With Pre-emphasis
20
40- & 38-Gb/s over 10m Coax
No Pre-emphasis
-23dB
200mVpp
Pre-emphasis @40Gb/s
200mVpp
Pre-emphasis @38Gb/s
21
Conclusions
Large swing, fully-differential 40-Gb/s SiGe BiCMOS
cable driver with adjustable pre-emphasis has been
presented.
Key features include:
Distributed pre-emphasis technique
MOS-HV-HBT cascode topology
Transmission experiments over Belden 1694A coax:
equalization of -24dB of loss at 5GHz
equalization of -22dB at 19GHz
Experimental results indicate that this driver could also
be used as a 50W EAM driver operating at 40 Gb/s.
22
Acknowledgements
Jazz Semiconductor and Marco Racanelli for fabrication
Gennum Corporation and NSERC for funding
Jaro Pristupa for CAD support
23
Backup Slides
24
Transmission Experiment over 10m, 30m
and 40m of Belden Coaxial Cable
Coax
RSH
DUT
Source
To Remote Sampling Head (RSH)
25
38- & 30-Gb/s over 10m Coax Cable
-17.7dB
30-Gb/s
26
20-Gb/s over 30m Coax Cable
-29dB
27
Measurement Bottlenecks
1. 75W cable driver to be measured in a 50W environment
Eventual packaging will solve this problem
2. How will S21 and S22 change when driving a 75W load
when compared to the 50W measurement?
S21 and S22 will improve in theory
3. How can we verify the maximum swing to be expected
in a 75W environment?
Theoretically the swing driving 75W should be 1.25 times the
swing driving 50W
28
Driver Output Impedance:
Measurements vs. Simulations
29
DCC Control @ 40- and 30-Gb/s
30
Choice of Technology
Considerations
CMOS
SiGe
90/65nm BiCMOS
III-V
System Integration
?
Low cost
High-speed (40Gb/s)
Output swing (5Vpp per side)
Reliability over temperature
?
40-Gb/s BiCMOS
Retimer in 90nmis
CMOS
65nm
for margin
SiGe
the– need
best
option
T. Chalvatzis, JSSC07
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Initial Driver Design
Driving a 75W coax cable with 5Vpp per side requires digital
switching of ~133mA
For reliable operation under large output voltage swings, high
voltage HBTs (HV-HBT) are required
at the output node
Vdd
BVCEO=3.5V
Vdd
fT = 75GHz
75W
fMAX = 100GHz
Line driver
75W
IT = 5Vpp / 37.5W
= 133mA
RC time constant analysis, when the HV-HBT is biased at
75W bandwidth of ~10GHz,
0.75*JpkfT, results in a -3dB
75W
Lumped toplogy is notVddan option therefore pointing to a
Vdd
distributed architecture (at least
for the output stage)
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Lumped Predriver Architecture
~3.3V
~3.3V
Vdd
Output Swing per side:
~3.3V
50W
300mV
INP
INN
3mA
50W
Input DC
1.1V - 1.8V
400mV
800mV
1V
Small Input Device to
5mAminimize
5mA capacitance
10mA
20mA
and
improve input matching
without EFs
DCC
Amplitude
Control
Offset
Control
1.2V
75W
~3.3V
~3.3V
1.1 - 1.8V
40mA
60W
DCC
75W
current
Vdd
600W
BiCMOS cascode used in the final two stages for stability
10mA
Topology is ideal for impelmenting amplitude control
33
40mA Output Stage
~5V
75W
75W
~3.3V
~3.3V
8 x 5.46mm HV-HBT
8 x 5.46mm
Digital
2mm x 66
L=0.18mm
34
T-Line Compensation
T-line section
• Distributed T-line inductors designed to absorb the load
capacitance from the DA stage
• minimize the impact on Z0, S21, and phase distortion
35