Case study: Integrating FV and DV in the Verification of Intel

®

Core

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2 Duo Microprocessor

Alon Flaisher Alon Gluska Eli Singerman Intel Corporation Israel Design Center

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Presentation Goals

• Share how the integration of FV with dynamic verification improved the productivity & quality of Merom verification • Highlight some of the barriers in effective deployment of FV • Update how FV is used in today’s CPU designs and what are the future challenges A. Flaisher

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Outline

• Challenges Applying FV in Merom • Our FV/DV synergy approach • Examples • Looking forward A. Flaisher

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Challenges in Applying FV in Merom

• Allocate resources for FV • Replace traditional dynamic verification (DV) activities • Choose the best designs to FV • Quickly establish new FV environments A. Flaisher

Our Approach – FV/DV Integration

5 • Replaced DV activities – For each DUT decided what would be the effect on DV – 75% of the proofs replaced DV activities, mainly coverage – Enabled allocating resources for FV • FV was also applied by VE (non FV experts) – Familiar with the design, owned both activities – Compared the complexity of the design vs. the proof – Provided more flexibility in assigning engineers to FV • FVE established FV environments for VE – Better utilized expertise • Joint decision where to apply FV • Joint test plans and checking A. Flaisher

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Example 1: ALU Cluster

• Independent execution units • FV done in 2 nd half of the project • Cluster level FV using symbolic simulation (STE/FL) – FVE built a Cluster Formal Environment – Active unit driven symbolically – Remaining units driven with X’s FAU

CFE

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• The unit owner (VE) coded the spec/checkers for each micro instruction in FL – Thousands of micro-instructions – Some are very simple to code, once you know the spec IEU AGU ...

MIU A. Flaisher

Example 1: ALU Cluster (Cont.)

7 • FV/DV approach provided much higher verification quality for comparable investment!

• Higher quality verification – 98% of the micro-instructions fully verified!

– Unit dependencies also verified –

Zero bugs found in silicon

• Reduction of effort – Done

instead

of coverage (which requires huge investment) • Good utilization of expertise – FVers built the CFE and carried out highly complex proofs – DVers wrote most specs FAU IEU AGU

CFE

...

...

A. Flaisher MIU

Example 2: MS Unit

8 • The MS unit – Translates instructions to uop sequences – Needs to support all combination of uops and events (any ROM) • Unit was completely FV by an expert VE – MS team chose FV as the main verification tool – Used BMC on unit boundaries – 1400 vars, bound 40 uip – Reference model for checking ROM uops IA instruction Decoders MS Unit Control Clears uops A. Flaisher

Example 2: MS Unit (Cont.)

9 • FV/DV provided much higher quality for less effort!

– FV found corner case bugs impractical for simulation – Prevented bugs from being released – Replaced most DV activities – Enabled by the MS validation team IA instruction uip Decoders ROM uops MS Unit Control Clears uops A. Flaisher

Looking Forward

• FV integration to mainstream verification continues to grow in current CPU designs – More FV resources in Sandy Bridge (Intel’s 2010 TOC) – Good acceptance throughout the project – Single spec language for RTL assertions and FV (SVA) – Aggressive ABV methodology improves assertion FV ROI – Sharing (unit level) checkers through SV reference-models Assertion FV RTL (SV) FV DV Reference Model (SV) Assertion FV 10 A. Flaisher

Looking Forward (Cont.)

• Good results from applying FV for bug-hunting – Integrate FV for bug hunting in early stages – Integrate FV to get highest confidence in later stages • Key capabilities are still missing – Sharing FV/DV environments – Unit level capacity – Solutions for system level properties – Predictability and complexity analysis – … 11 A. Flaisher

Q&A