Display Hardware Yingcai Xiao Printers Dot Size: dpi (dot per inch). 300, 600, 1200, … Dot Distance.

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Transcript Display Hardware Yingcai Xiao Printers Dot Size: dpi (dot per inch). 300, 600, 1200, … Dot Distance.

Display Hardware Yingcai Xiao

Printers

Dot Size: dpi

(dot per inch). 300, 600, 1200, …

Dot Distance.

Printers

 

Types:

Dot-matrix:

Printer head has 7x7 ~ 24x24 pins.

Pen plotter:

Drawing with mechanical pens.

Laser printer

: position-charged rotating drum, laser beam hits the parts to be white, discharge the areas, negatively charged powered toner adheres to the positively charged area.

Ink-jet printer

: sprays cyan, magenta, yellow and black ink onto paper.

Thermal-transfer

: Colored wax-paper ==> plain paper 

Thermal-sublimation dye transfer:

 256 intensities for each C, M, Y==>16M colors.

Near-photographic

Camera

Film recorder

Display Technologies 1) B/W CRT

(Cathode Ray Tube): Cathode ray hits phosphor, which in turn emits light.

Phosphor Persistence

: time of decay after electronic excitation. (Can’t be too short or too long.) 

Critical Fusion Frequency

CFF > 60 frames/second.

Bandwidth

of a monitor depends on how fast the electron gun can be turned on and off.

n pixels / scan line ==> on/off n times per scan line 1000 pixels / line * 1000 line /frame * 60 frames / s  16 nanoseconds / switch.

2)

Color CRT

 3 guns: RGB  Triad phosphor dots: RGB   One gun: Sony Trinitron ( http://en.wikipedia.org/wiki/Trinitron )

3) Projection CRT (for large-screen) 4)

LCD: liquid-crystal display

(light weight)  raster, grid-like  lighting at point (x, y) changes when voltage is applied at the point.

 Active Matrix: emitting light  Passive: reflecting light 5) LED: light-emitting diode (http://en.wikipedia.org/wiki/LED) 4) PDP: Plasma Display Panel http://en.wikipedia.org/wiki/Plasma_display

Raster-Scan Display Systems A simple raster system

CPU Peripheral Device System Bus System Memory Frame Buffer Video Controller Display

The Video Controller

The most important task for the controller is the constant refresh of the display (60 frame per second) 1) Interlaced 1 st field: odd lines 2 maps. nd field: even lines 2) Non-interlaced: updates every scan-line in every field 3) Output: RGB, monochrome, NTSC (video tape) 4) Sprites in animation: a sequence of fixed-size pixel 5) Video Mixing: 6) FB + External Video --> VC --> display

Frame Buffer

: memory that stores the color data for each pixel on the screen.

Video controller reads

the color value for each pixel and controls the intensity of the display at the pixel.

Memory Speed Problem

: 1K pixels / line  1K lines / frame  60frame / second  60 million reads/second ==>16 ns per read RAM speed ~ 50 ns/read ?

Interlacing

odd and even lines.

VRAM

: Video RAM (TI), reads all the pixels on a scan line in one cycle.

Frame Buffer Depth

Number of bits for each pixel (n).

Also called number of planes.

Number of possible colors: 2 n

VRAM size >= screen resolution * depth 24 bits

: 16 M colors,

True Color

 1K  1K  3 bytes =3MB VRAM    1K  768  3=2.3MB

800  600  3=1.5MB

640  480  3=1MB

32 bits

: RGBA, 16 M colors + Transparency (“Highest” in Windows)

16 bit

:

Pseudo True Color

, 64K (“Medium” in Windows)  1K  1K  2=2MB VRAM   1K  768  2=1.5MB

800  600  2=1 MB  640  480  2=0.6 MB 8 bit: Indexed Color, 256, SVGA   1K  1K  1=1MB VRAM 800  600  1=0.5MB

Look-up Table for Indexed Color

With indexed colors, pixel values represent the index number into the LUT. The corresponding data value in the LUT represent the colors. •8 bits / pixel => 256 colors at a time.

•12 bit / entry => 4k colors to chose the 256 from.

 GPU (Graphics Processing Unit) Peripheral Device CPU System Bus Display Processor System Memory Graphics Controller Display Processor Memory Frame Buffer Video Controller Display • Specialized hardware to assist graphics display operations. (scan-convert, bitblt) • More to come on GPU and GPGPU.

Graphics Pipeline

 Process objects one at a time in the order they are generated by the application  Pipeline architecture 17  display All steps can be implemented in hardware on the graphics card E. Angel and D. Shreiner: Interactive Computer Graphics 6E © Addison-Wesley 2012

OpenGL Architecture

Immediate Mode geometry pipeline

Polynomial Evaluator Per Vertex Operations & Primitive Assembly CPU Display List Rasterization Per Fragment Operations Frame Buffer Pixel Operations Texture Memor y

Angel: Interactive Computer Graphics 5E © Addison-Wesley 2009 18