Transcript EE141 Project: Register File Adam Abed Register Cell Design BLW1      Minimum size storage inverters Combined gate read transistors Wordline contacts on edge of cell to reduce spacing Shared.

EE141 Project: Register File
Adam Abed
Register Cell Design
BLW1
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Minimum size storage inverters
Combined gate read transistors
Wordline contacts on edge of
cell to reduce spacing
Shared VDD and GND rails
between adjacent cells
Area : 52.07 µm2
Kenneth Duong
Register Cell Operation
BLW2
Decoder Schematic and Sizing
VDD
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WLW2
Write Margin : 0.89 V
Bitline voltage at which write NMOS can
not over power the storage inverters
Margin High : 1.08 V
Margin Low : 0.89 V
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WLW1
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Read Margin
Storage node to the gate of the read
transistor
Only noise during a write will result in
an invalid read: Read Margin = Write
Margin
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WLR2
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WLR1
WLR3
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Worst Case: Three read wordlines high
Simulated with a 20fF load on each
bitline
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Register Cell Schematic
BLR2
Register Cell Layout
Decoder Layout
BLR3
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4:1
2:4
2:6
Logical Effort
5/6
1
8/6
Intrinsic
Delay
5/6
8/6
2
Logical Effort and Intrinsic Delays
Optimize LH Transition of the Word Line Through Sizing
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Doubling the size of the PMOS on our inverters (LH switching on the path)
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Doubling the size of the NMOS on our NAND gates (HL switching on the path)
GND
Decoder Simulations
STAGE5
INV
Sizing Ratio
(P:N)
Critical Decoder Path Schematic
Read Current : 167µA
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BLR1
Inverter 2-NAND 3-NAND
(LH)
(HL)
(HL)
Register File Peripheral Design
Design Choices:
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Minimum-sized Precharge Transistors
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Decoder Simulation Comparison
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8:2 Output Inverters
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STAGE3
INV
STAGE4
3NAND
Pre-design Simulation
STAGE2
2NAND
STAGE2
3NAND
STAGE1
INV
Register File Layout
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DATA INPUTS - A1
Stage 1 Delay
61.28
81.41
Stage 2 Delay
Stage 3 Delay
70.71
92.46
118.94
98.70
Stage 4 Delay
Stage 5 Delay
72.50
102.57
79.48
119.95
Total Delay
399.41
498.49
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PRECHARGE
TRANSISTORS
INPUT
INVERTERS
4:1 Input Inverters
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Needed to complement output inverters
Limit input capacitance to 5fF
OUTPUT
INVERTERS
Datapath Schematic
Register File Write Simulation
Register File Read Simulation
16x16 CELL BLOCKS
DATA INPUTS - A1
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Simulated writes into register 0
Input rise and fall times constrained to
50ps
Write-0
ADDRESS LINES
DATA OUTPUTS - A1
Write-1
Read-1
Write-1

DECODER
Simulated
Delay (ps)
200 ps output rise time requirement
Minimize LtoH delay of output
Extracted Simulation
ENABLES
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DATA OUTPUTS - A1
Pre-Design
Delay (ps)
Since clock speed is not an issue, this
design saves area


Input rise and fall times
constrained to 50ps
Storage node shown is
complement of input value
Rise Time : 190.66 ps
Simulated Write of Register0 Bit0
Write
Delay
Total
Delay
Simulated Read of Register0 Bit0
Read-0
Operation
Decoder
Delay
Write-1
463.58 ps
49.74 ps 513.32 ps
Read-1
463.58 ps 251.19 ps 714.77 ps
Write-0
463.35 ps 659.67 ps 1143.0 ps
Read-0
463.38 ps
Operation
Decoder
Delay
Write
Delay
x
Total
Delay
463.38 ps