Transcript RMO4C-2 A Low-Noise 40-GS/s Continuous-Time Bandpass ΔΣ ADC Centered at 2 GHz Theo Chalvatzis and Sorin P.

RMO4C-2
A Low-Noise 40-GS/s
Continuous-Time Bandpass ΔΣ ADC
Centered at 2 GHz
Theo Chalvatzis and Sorin P. Voinigescu
The Edward S. Rogers Sr.
Department of Electrical and Computer Engineering
University of Toronto
Toronto, Canada
Outline
• Motivation
• ADC system level architecture
• Circuit design
• Measurements
• Conclusion
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Motivation
• Direct sampling receiver for 2-GHz CDMA basestation
• Transistor fT of 150..250 GHz and low-BVCEO naturally point to
1-bit ΔΣ digitization of RF signal
• Continuous-Time Bandpass ΔΣ topology offers:
– Higher resolution and lower power than other ADC types
– Low complexity (simple layout is important at 40 GHz!)
– LNA as input stage
Digital Receiver
LNA
Duplexer/BPF
TO DSP
High-Speed ADC
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System Level Architecture
• 2-GHz Gm-LC BPF
BPF2
LNA & BPF1
• 1-bit quantizer as DFF
2GHz BPF
2GHz BPF
RF
INPUT
Gm2
Gm1
DFF
DRIVER
DIGITAL
D
Q
• RZ pulse DACs
OUTPUT
• Loop design in sdomain
RZ
DAC1
Gfb1
Gfb2
RZ
DAC2
CLOCK
TREE
Gm1Gm2
C2 
H(s)=
s2
2
2
 s +ωo 


2
DAC(s)




2
Gfb1Gm2
 Gfb2

s
s
1+ 
+
DAC(s)
2
2
2
C
 C  2




2
2
2
 s +ωo 
 s +ωo  




 

CLOCK
Fs=40GHz
DAC(s) the TF of RZ DAC
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New Loop Filter Topology
2GHz BPF
2GHz BPF
RF
INPUT
Gm2
Gm1
DFF
VCC (2.5V)
DRIVER
DIGITAL
D
LC
Q
OUTPUT
RZ
DAC1
Gfb1
Gfb2
RZ
DAC2
CC
FEEDBACKP
FEEDBACKN
CVAR
CLOCK
TREE
CLOCK
VTUNE
VB
Fs=40GHz
• MOS-HBT cascode provides:
– Linearity and low-noise
with no degeneration
– Lower power supply
(VGS<VBE)
• Bias at peak-gm current
density for maximum linearity
VB
INN
INP
LE
LE
LEE
Zo
LE for input 50Ω matching: LE = ω
T
LEE for common mode rejection
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New RZ DAC Topology
2GHz BPF
2GHz BPF
RF
INPUT
Gm2
Gm1
DFF
DRIVER
DACP
DIGITAL
D
Q
DACN
OUTPUT
RZ
DAC1
Gfb1
Gfb2
VCC (2.5V)
RZ
DAC2
DFFP
Q1
Q2
DFFN
Q3
Q4
VB
CLOCK
TREE
CLOCK
Fs=40GHz
CLKP
M1
M2
• DAC with RZ pulse for
immunity against loop delay
• Higher switching speed due to
MOS-HBT cascode
CLKN
ITAIL
VGTAIL
M3
• High gm/ITAIL ratio (due to HBT)
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New 40-GHz Quantizer Topology
VCC (2.5V)
2GHz BPF
2GHz BPF
RF
INPUT
Gm2
Gm1
DFF
DRIVER
DIGITAL
D
Q
OUTPUT
RZ
DAC1
Gfb1
Gfb2
RZ
DAC2
INP
CLOCK
TREE
CLOCK
INN
CLKP
OUTP
CLKN
OUTN
Fs=40GHz
• MOS-HBT MSM flip-flop:
V
– 3 latches to compensate for
metastability
Min swing at quantizer input: 10mVpp
– MOS on clock path to
3 stages needed for full logic swing
improve speed with low
(300mVpp) at DAC input
supply
– HBT on data path for high
gain
G
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40-GHz Bandwidth Clock Distribution
2GHz BPF
2GHz BPF
RF
INPUT
Gm2
Gm1
DFF
DRIVER
DIGITAL
D
10.8mA
33.8mA
EF-INV
EF-INV
44.4mA
Q
TO DACs
(ILOAD=60mA)
EF-INV
OUTPUT
RZ
DAC1
Gfb1
Gfb2
EXTERNAL
CLOCK
RZ
DAC2
EF-INV
EF-INV
58.6mA
TO DFF
(ILOAD=62mA)
EF-INV
CLOCK
TREE
44.4mA
CLOCK
65.2mA
Fs=40GHz
VCC (2.5V)
• External clock distributed to 3
latches and 2 DACs
• EF-MOS-HBT cascode for
increased bandwidth and
large capacitive load drive
OUTN
OUTP
VCC
INP
VCC
VB
VB
INN
VG
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Fabrication and Characterization of
loop filter breakout and ADC
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115mW
2GHz BPF
ADC Die Photograph
2GHz BPF
RF
INPUT
Gm2
Gm1
DFF
DRIVER
DIGITAL
D
Q
OUTPUT
62.5mW
175mW
RZ
DAC1
512.5mW
94mW
RZ
DAC2
645mW
CLOCK
• ADC and filter breakout fabricated in
STM’s 0.13μm SiGe BiCMOS:
– HBT fT/fmax=150/160 GHz
– 2μm finger width n-MOSFET
fT/fmax=80/90 GHz
1.52x1.58mm2
• Total power dissipation 1.6W from 2.5V
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Loop Filter – Measurements
• Linearity and noise measured on a filter test structure
• Optimum bias point for maximum linearity: 0.4mA/μm
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ADC – S-parameters
Single-ended measurements
• Q=17 and BW3dB=120MHz
• ADC stable up to 65GHz
• S22<-7dB up to 65GHz and <-15dB up to 22GHz
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ADC – Spectrum Measurements
Single-tone at 2-GHz ON
Single-tone at 2-GHz OFF
• No idle tones present in-band
• Inset shows > 35dB/dec noise shaping
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ADC – SNDR Measurements
• SNDR measured with
Spectrum Analyzer
• Resolution BW lowered
until noise floor
remained constant
(RBW < 50 KHz)
• Measurements taken for
bandwidths between
1 MHz and 120 MHz
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ADC – SNDR vs BW Measurements
• SNDR=55dB over 60 MHz
• SNDR=52dB over 120 MHz
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ADC – SFDR Two-Tone Measurements
• Two-tone test with
2 GHz RF inputs at
10 MHz spacing
• PIN= -30dBm
• SFDR=61dB
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ADC – 40-Gb/s Eye Diagram Jitter
Measurements
• 2-GHz input sinusoid
• Feedback turned-off
• JitterRMS=375fs
• Jitter does not affect
ADC resolution
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ADC Performance
Center Frequency
Clock Rate
OSR
SNDR
2 GHz
40 GHz
333
55dB/60MHz
52dB/120MHz
SFDR
61 dB
Power Supply
2.5 V
Power Dissipation 1.6 W
FOM
18 pJ/bit
Ref
[2] (BP)
[3] (BP)
[4] (BP)
[6] (LP)
This work
Figure of Merit (FOM) definition
(lower
better):
PDC
FOM  ENOB
2
2BW
Process
Fs (GHz) Fc (GHz) BW (MHz) SNDR (dB) FOM (pJ/bit)
Si
3.8
0.95
0.2
49
1473
InP
3.2
0.8
25
41
400
InP
4
1
60
47.4
135
InP
8
62.5
57.4
24
SiGe BiCMOS
40
2
60
55
26
40
2
120
52
18
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Conclusion
• First mm-wave sampling ΔΣ ADC in any
technology (> 2xFs)
• Direct RF A/D Conversion at 2-GHz with 9-bit
resolution over 60 MHz
• 11 bits over 60 MHz possible in this topology with:
– Improved filter linearity
– Higher filter Q
• Best FOM among all ADCs with clocks > 1 GHz
• 40-48 GS/s design scalable to 3.5/5/12 GHz
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Acknowledgements
• Eric Gagnon and Morris Repeta for system
performance specifications
• Nortel Networks for funding support
• STMicroelectronics for chip fabrication
• ECTI for lab access
• CMC for CAD tools
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