Transcript Toward Nano-Networks and Architectures C. Gerousis and D. Ball Department of Physics, Computer Science and Engineering Christopher Newport University Newport News, VA 23606 Gerousis.

Toward Nano-Networks and
Architectures
C. Gerousis and D. Ball
Department of Physics, Computer Science and Engineering
Christopher Newport University
Newport News, VA 23606
Gerousis
Nanoelectronic Architectures
• Limits of Conventional CMOS technology
- Device physics scaling, power dissipation
- Interconnects
• Nanoelectronic Integrated Circuits
- Hybrid circuits of ultrascale CMOS coupled to locally connected
cellular nonlinear networks (CNNs) of nanodevices for special
purpose processing
• Present Work
-Simulation of nano networks synthesized from single-electron
tunneling transistors (SETs)
-Demonstration of SET-CNN and SET neural applications
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Nanoelectronic Integrated Circuit
Photo-detector
Single-electron transistors
as processing elements
CMOS drivers for fan-out
CMOS and SETs are rather complementary: SET is the winner of low-power
consumption and of new functionality while the advantages of CMOS such as
high-speed, driving, voltage gain and input impedance can makeup for
exactly for the SET's intrinsic shortcomings.
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Single-Electron Transistor
A single-electron tunneling (SET) transistor composed of a
conducting island (or quantum dot) between two tunnel
junctions characterized by junction capacitances, Cs and Cd,
and tunneling resistances, Rs and Rd.
R,C
d
d
n1
island
drain
Va +
_
R,C
s
s
n2
source
Cg
gate
Vg +
_
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Single-Electron Transistor
Electron tunneling is suppressed due to the Coulomb charging
energy, e2/2C. A separate gate voltage changes the charge
state of the dot (island), and periodically lifts the Coulomb
blockade allowing tunneling.
G/Gmax
e
1
EFl
0
0
1
2
3
EFr
Vg (e/Cg)
Si SOI Single Electron
Transistor:
D. H. Kim et al., IEEE
Trans. ED 49, 2002
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Monte Carlo simulation of SET circuits
The Master Equation for a set of N dots (islands) in terms of
the multi-island distribution function is given by
df n1 , n2 ,...,nN , t 
    n1 ,...ni  1 f n1 ,..ni  1, t  
dt
i 1, N


   n1 ,...ni  1 f n1 ,..ni  1, t     n1 ,...ni     n1 ,...ni  f n1 ,..ni , t 
where the tunneling rate depends on change of total free
energy of systems after tunneling
1 En / e
 n 
 En / kT
eRtj 1  e

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Monte Carlo simulation of SET circuits
Average quantities such as current in a two junction system are given as
averages
I (V )  e

 f (n)[ (n)   (n)] 
n  

2

2



f
(
n
)
[

(
n
)



1
1 (n)]
n  
Single electron tunnel events modeled as instantaneous events which are
generated stochastically using the calculated tunneling rates for all possible
events across all junctions, and using the computer random number generator
tr 
- ln(r )
.....   j

j
where r is random number 0,1 and tr is the random time between tunneling
events. After tunneling, the new tunnel rates are computed, and the next
tunneling event generated. The time evolution according to the master
equation is modeled as random walk.
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‘SIMON’ (SIMulation Of Nano structures)
C. Wassshuber and H. Kosina, "SIMON: A Single-Electron Device and Circuit Simulator", Superlattices and
Microstructures 21, 37 (1997).
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SET Cellular Nonlinear Networks
A non-linear architecture suitable for SET devices is a locally
interconnected CNN type array structure for use in array processing such
as image processing applications. The center cell, Cij, receives a weighted
feedforward signal bklukl and a weighted feedback signal aklykl from each
neighboring cell Ckl.
aklykl
xij
xij klukl
b
Feedback synapses
Feedforward synapses
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Cellular Nonlinear Networks
Cell state equation:
dxij
dt
Cell output equation:
  xij   aij yij   bijuij  zij
ij
ij
1,

1
yij  f ( xij )  xij  1  xij  1   xij
2

- 1,


xij  1
xij  1
xij  1
y
1
Transfer function:
x
-1
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Single-Electron Cellular Network - Shadowing
C
2
1
C
3
2
C
1
1
C
2
2
V
in
1
Template:
C12=C
=0.55aF
V
23b
o
u
n
d
a
r
y
L
V
in
2
V
o
u
t1
V
b
o
u
n
d
a
r
y
R
V
V
3
o
u
t2 in
C11=C22= C22=0.1aF
C
1
2
C
2
3
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Threshold Gate in SET Networks
 A threshold gate can be
described by the following
equations:
0 if G ( x)  0
F ( x)  sgn{G ( X )}  
1 if G ( x)  0
n
G ( X )   ixi 
i 1
where ω are the weights, x
represents the inputs, and
ψ is the threshold
Model of a TLG with SET technology (Lageweg et al.)
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Threshold Gate - SET inverter
Model of a TLG with SET technology (Lageweg et al.)
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Network for Recognition of Bit Pattern
1111
1001
V1
V2
V3
V4
Vout
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Network for Recognition of Bit Pattern
1000
0001
V1
V2
V3
V4
Vout
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Number Recognition Sub-Networks
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Number Recognition Test Circuit
The network contains several
levels/layers of hidden
operations between input and
output. These layers include
row detection, number
recognition, and encoding.
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Number Recognition Test Circuit
Input Matrices for V0-V19:
M1
M2
M2
M
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S1 S0
0
0
0
1
0
1
2
1
0
≥3
1
1
M3
18
M4
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Number Recognition Network – Results
2.00E-02
1.60E-02
1.60E-02
1.20E-02
1.20E-02
8.00E-03
8.00E-03
4.00E-03
4.00E-03
00
0.00E+00
0.00E+00
2.00E-02
2.00E-02
1.60E-02
1.60E-02
1.20E-02
1.20E-02
8.00E-03
8.00E-03
4.00E-03
4.00E-03
10
0.00E+00
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0.00E+00
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Conclusions
• A neural nanoelectronics architecture with a low
interconnection density, such as cellular neural networks
(CNNs) are implemented in analog circuit techniques so that
low power applications, such as intelligent sensor preprocessing are preferred applications.
• Limitations:
- Small capacitance values required for roomtemperature operation.
- SET weights are hard wired by the use of capacitive
connections, which limits the range of applications.
- The charge sensitivity of the devices also imposes
strong limitations on the allowable electrostatic
interaction between different devices in a ULSI circuit.
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