Transcript Memory - 2 10/27/08 ECE 561 - Lecture 13 Memory 2 Memory • The internal structure of the ICs • ROM Types and RAM 10/27/08 ECE.

Memory - 2
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ECE 561 - Lecture 13 Memory 2
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Memory
• The internal structure of the ICs
• ROM Types and RAM
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Memory Types
• How a ROM works
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A 128 x 1 ROM
• The basic
structure
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Larger Array Sizes
• Arranged in blocks
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Commercial ROM Types
• Table 9-5
– Type Tech ReadCyc WrCyc
Comments
–
–
–
–
–
–
–
–
–
Write once, low pwr
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MASK ROM NMOS 10-100ns
CMOS
MASK ROM Bipolar <100ns
PROM
EPROM
EEPROM
4 weeks
4 weeks
Write once, h pwr
low density
Bipolar <100ns 10-50us/byte Write once, h pwr
NMOS 25-200ns 10-50us/byte Reusable, low pwr
CMOS
NMOS 50-200ns 10-50us/byte 10,000 to 100,000
writes per location
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EPROM
• Erasable Programable Read Only Memory
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EPROM
• Uses a floating gate for the FET at each bit location
• User uses a programming voltage that causes a
temporary breakdown in the dielectric between the
gate and the floating gate to charge it.
• When programming voltage is removed the charge
stays
• How long? EPROM manufacturers “guarantee”
properly programmed bit has 70% of charge after 10
years.
• Use UV light to erase
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EEPROM
• Electrically Erasable PROM
• Like the EPROM only electrically erasable in
circuit.
• Many times referred to a “flash”
programmable memory
• Very slow on writes so not a substitute for
RAM
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General Block Diagram
• xROM
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General Timing
• General timing parameters
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The timing parameters
•
•
•
•
•
Access time from address – tAA
Access time from chip select - tACS
Output-enable time - tOE
Output-disable time - tOZ
Output-hold time - tOH
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R/W Memory
• Memory to store and retrieve data when more
than F/Fs
• A few types
• Static RAM – SRAM
– As long as power is maintained data is held
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SRAM
• The data storage
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A static RAM chip
• Internal – an
arrangement of
storage sturctures
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SRAM Timing
• Timing for write similar (see Fig 9-23)
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DRAM
• Next step in memory is Synchronous SRAM
which has a clocked interface for control,
address and data.
• Then comes DRAM – dynamic ram
Bit line
• In DRAM data is stored
Word line
• in a semiconductor
• capicator.
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DRAM Read
• A read sees the bit line precharged to high.
• The word line is then activated
• If cell stores a 0 then there is a small drop on
the voltage on the bit line
• This is monitored by a sense amp which
provides the value stored
• Value must be written back after the read.
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DRAM Refresh
• Charge stored leaks off over time
• Must restore the values stored
– A 4096 row DRAM – refresh every 64ms
– Thus each row every 15.6 usec
• Larger DRAMs are banks of smaller
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DDR SDRAM
• Double data rate SDRAM
• Double the data transfer rate of an SDRAM by
transferring on both edges of the clock
• Access and setup times are the same as SRAM
• Increased data thruput as data is transferred
in blocks.
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