Transcript Observations in Characterizing a Commercial MNOS EEPROM for Space E. E. King, R.

Observations in Characterizing a
Commercial MNOS EEPROM for
Space
E. E. King, R. C. Lacoe, G. Eng, and M. S. Leung
The Aerospace Corporation
El Segundo, CA
(310) 336-7898, [email protected]
2004 MAPLD International Conference
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 8-10, 2004
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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P/MAPLD 2004
Hitachi HN58C1001
Specification
• 128k x 8-bit (1 Mbit) Electrically Erasable and
Programmable Non-Volatile Memory
• Single 5 V Power Supply (-10V programming
voltage generated on chip)
• Access Time 150 ns
• Automatic Byte or Page (128 bytes) Write
• Write Time <10 ms
• 104 Erase/Write cycles
• 10 year Data Retention
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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MNOS Memory Transistor
Operation
•
•
•
•
•
Presence or absence of charge
trapped in the silicon nitride layer
results in a change in Vth between
two states defined as a ‘1’ and ‘0’
Electrons are injected (write a ‘1’)
by setting Vg = 5 V with -10 V
applied to the well
N+ Source
A ‘1’ is erased (write a ‘0’) by
applying 5 V to the well and setting
Vg to -10 V, which injects holes
The transistor state is interrogated
by detecting channel current for a
Vg = 0 V
Data loss is generally due to
thermal emission of the trapped
charge in the silicon nitride (Ea =
1.1 eV)
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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Gate
28 nm Si3N4
P well
1.6nm SiO2
N+ Drain
N substrate
P/MAPLD 2004
Typical Space Application
• Memory written at beginning of mission
• No power applied until the memory is
needed to re-initialize the system
• No memory rewrite planned during the
mission
• Memory speed is not critical
• Maximum temperature is 70 C
• Data must be retained for 15 years
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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Our Test Objectives
• Determine data retention lifetime
– Stress parts at high temperature to accelerate data loss
– Stress at two temperatures to determine the activation
energy for the data loss process
– Use data to predict data retention lifetime at 70 C
– Characterize effect of TID on data retention
• Develop qualification test to screen potential early
failures out of the production part population
– Determine worst-case test parameters
– Develop worst-case test pattern
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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Accelerated Aging Test Plan
• Pre-condition parts
– Write checkerboard and inverse checkerboard 220 times
– Soak at 150 C for at least 48 hours
• Age at 175 and 200 C - all leads grounded
– Epoxy package material verified to be OK to >250 C
– Half population written with checkerboard/half with
inverse checkerboard
– Parts tested at short intervals to catch early/intermittent
failures (every 4 hours @ 200 C, 22 hours @ 175 C)
• Determine impact of TID on aging
– Irradiate parts to 78 krad in 26 krad steps (Co-60)
– Repeat aging test post-radiation to assess affect of TID
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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• Thermal stress produces
a push-out of the read
access time
• The access time returns
to its initial distribution
after rewrite
• Push-out extrapolated to
150 ns to estimate timeto-failure
• Aging data at 175 and
200 C used to determine
activation energy
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
No. of Data Byte Errors
Aging-Induced Push-Out of
Read Access Time
40000
Control-Q2
553 hours
951 hours
1036 hours
1305 hours
Rewritten
30000
20000
10000
0
70
75
80
85
90
95
100
CE Access Time (ns)
Part Thermally Stressed at 200 C
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Data Retention Lifetime
• Assume that access time push-out is caused by charge
leakage off the memory transistor
– Push-out also might be influenced by the initial charge
stored on the transistor and variations in sense amps
• Error distribution vs. access time at 226 hours @ 200 C is
similar to that at 1305 hours @ 175 C
– Corresponds to an activation energy of 1.2 eV
– Estimated time-to-failure (150 ns) at 70 C is a few
hundred years
• Worst-case activation energy for charge detrapping in the
MNOS structure found in the literature is 0.35 eV
– Estimated time for access time to reach 150 ns at 70 C
based on this activation energy and our access-time pushout data is about 50 years
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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Results of TID Tests
• No significant degradation in performance
found after 78 krad(Si) irradiation (unbiased)
• Aging experiments after TID at 175 and 200 C
showed the same access time push-out as had
been measured in the initial aging experiments
to within about 2%
• Caution: The on-chip high voltage bias
generator fails at 10-to-20 krad when
irradiated under normal operating voltages
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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Signature of Intermittent
Readout Failure
OE
• Intermittent failure observed during
0
aging due to oscillations on data
I/O1
outputs
1
– Not clear that increasing readout I/O2
access time will solve problem
CE
• Oscillations worse as Vdd is
Normal Waveforms
decreased
OE
• Oscillations disappear as
temperature increased to 38C
I/O1
• Oscillation occurs long before there
is a data retention problem due to
I/O2
aging
• Oscillations spontaneously disappear CE
in minutes to hours
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appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
Output oscillations
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No. of Bit Errors
Parametric Testing -- Effect
of Ambient Temperature
40
Vdd = 5.0V
30
tce = 150 ns
20
10
0
0
20
40
60
80
Temperature (C)
• Number of errors decrease as the ambient temperature is
increased
• Recommend testing at below room temperature to increase
probability of detecting a ‘weak’ part
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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Test Pattern Sensitivity
• A bit failure was estimated to be 26,000 times
more likely to be a ‘0’ than a ‘1’
• The worst-case pattern resulting in an error was
reading a byte with all ‘0’s after reading a byte
with all ‘1’s (70% of failed patterns)
Data Pattern Written
11111111
00000000
Data Read Example
11111111
00111111
Error
• Percentage of failed patterns decreased as the
numbers of ‘1’s in the prior byte decreased
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appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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P/MAPLD 2004
Test Pattern Developed to
Screen out Weak Parts
• Pattern heavily populated with ‘0’s (over 98%) to
increase probability of finding an early failure
• Short sequence of patterns inserted periodically in
the address space to detect pattern sensitive failures
• Unique data byte inserted when each address bit
first went high to ensure that each address bit
toggled
• New pattern estimated to be 300 times more likely
to detect an error than a checkerboard pattern
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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Conclusions
• Data Retention Lifetime found suitable for space
– Activation energy determined to be about 1.2 eV,
consistent with manufacturers value
– Worst-case data retention time estimated to be about
50 years
• Found no TID problem up to 78k rad(Si) for
unbiased irradiation
• Identified a small probability for early failure
due to data output oscillation
– Consider operating part at Vdd>5V to eliminate oscillations
– Oscillations also eliminated when operated somewhat above
room temperature
– Unclear that extending the readout access time can ensure
correct data readout
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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Conclusions (cont.)
• Qualification test developed to increase
probability of identifying ‘weak’ parts
– Include tests conducted under worst-case
parametric conditions for intermittent failure
• Low Vdd
• Low Temperature
– Use special test patterns
• High percentage of ‘0’s
• Data patterns that include transitions from words with
high number of ‘1’s to words containing high number of
‘0’s for every sense amplifier
– Recommend eliminating any part exhibiting
behavior that is inconsistent with the general
population
King Permission to copy or reprint is not required, but
appropriate credit must be given to The Aerospace
Corporation for the generation of this material..
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