Transcript Sequential Logic  Sequential Circuits Simple circuits with feedback Latches Edge-triggered flip-flops  Timing Methodologies  Cascading flip-flops for proper operation  Clock skew  Basic Registers Shift registers Counters CS.

Sequential Logic
 Sequential Circuits
Simple circuits with feedback
Latches
Edge-triggered flip-flops
 Timing Methodologies
 Cascading flip-flops for proper operation
 Clock skew
 Basic Registers
Shift registers
Counters
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Sequential Circuits
 Circuits with Feedback
Outputs = f(inputs, past inputs, past outputs)
Basis for building "memory" into logic circuits
Door combination lock is an example of a sequential circuit
State is memory
State is an "output" and an "input" to combinational logic
Combination storage elements are also memory
new
equal
reset
value
C1
C2
multiplexer
C3
mux
control
comb. logic
state
comparator
equal
open/closed
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clock
Circuits with Feedback
 How to control feedback?
What stops values from cycling around endlessly
X1
X2
•
•
•
Xn
switching
network
Z1
Z2
•
•
•
Zn
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Simplest Circuits with Feedback
 Two inverters form a static memory cell
Will hold value as long as it has power applied
"1"
"stored value"
"0"
 How to get a new value into the memory cell?
Selectively break feedback path
Load new value into cell
"remember"
"data"
"load"
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"stored value"
Memory with Cross-coupled Gates
 Cross-coupled NOR gates
 Similar to inverter pair, with capability to force output to 0
(reset=1) or 1 (set=1)
R
Q
S
Q'
Q
R
S
 Cross-coupled
NAND gates
 Similar to inverter pair, with capability to force output to 0
(reset=0) or 1 (set=0)
S'
R'
Q
S'
R'
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Q
Q'
Timing Behavior
Reset
Hold
R
Q
S
Q'
Set
Reset
Set
100
R
S
Q
\Q
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Race
State Behavior of R-S latch
 Truth table of R-S latch behavior
S
0
0
1
1
R
0
1
0
1
Q
hold
0
1
unstable
Q Q'
0 1
Q Q'
1 0
Q Q'
0 0
Q Q'
1 1
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Theoretical R-S Latch Behavior
SR=10
SR=00
SR=01
SR=01
Q Q'
0 1
SR=01
Q Q'
1 0
SR=10
SR=11
 State Diagram
 States: possible values
 Transitions: changes
based on inputs
SR=11
SR=01
possible oscillation
between states 00 and 11
Q Q'
0 0
SR=11
SR=00
SR=11
SR=00
SR=10
Q Q'
1 1
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SR=00
SR=10
Observed R-S Latch Behavior
 Very difficult to observe R-S latch in the 1-1 state
One of R or S usually changes first
 Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"
Or non-deterministic transition
SR=10
SR=00
SR=01
SR=01
Q Q'
0 1
SR=01
Q Q'
1 0
SR=10
SR=11
SR=11
SR=00
Q Q'
0 0
SR=11
SR=00
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SR=00
SR=10
R-S Latch Analysis
 Break feedback path
R
Q
Q(t)
Q(t+)
S
Q'
S
S
0
0
0
0
1
1
1
1
R
0
0
1
1
0
0
1
1
Q(t)
0
1
0
1
0
1
0
1
Q(t+)
0
hold
1
0
reset
0
1
set
1
X not allowed
X
R
S
Q(t)
0
0
X
1
1
0
X
1
R
characteristic equation
Q(t+) = S + R’ Q(t)
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Gated R-S Latch
 Control when R and S
inputs matter
Otherwise, the
slightest glitch on R
or S while enable is
low could cause
change in value
stored
R
R'
Q
enable'
Q'
S'
Set
S
100
Reset
S'
R'
enable'
Q
Q'
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Clocks
 Used to keep time
Wait long enough for inputs (R' and S') to settle
Then allow to have effect on value stored
 Clocks are regular periodic signals
Period (time between ticks)
Duty-cycle (time clock is high between ticks - expressed as %
of period)
duty cycle (in this case, 50%)
period
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Clocks (cont’d)
 Controlling an R-S latch with a clock
Can't let R and S change while clock is active (allowing R and
S to pass)
Only have half of clock period for signal changes to propagate
Signals must be stable for the other half of clock period
R'
R
Q
clock'
S'
Q'
S
stable changing stable changing stable
R' and S'
clock
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Edge-Triggered Flip-Flops
 More efficient solution: only 6 gates
sensitive to inputs only near edge of clock signal (not while high)
D’
D
holds D' when
clock goes low
negative edge-triggered D
flip-flop (D-FF)
0
R
4-5 gate delays
Q
Clk=1
must respect setup and hold time
constraints to successfully
capture input
Q’
S
0
holds D when
clock goes low
D
D’
characteristic equation
Q(t+1) = D
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Edge-Triggered Flip-Flops (cont’d)
 Step-by-step analysis
D’
D’
D
D
D’
R
D’
R
Q
Clk=0
Clk=0
S
S
D
D
Q
D’
when clock goes high-to-low
data is latched
D
D’
new D
new D  old D
when clock is low
data is held
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Edge-Triggered Flip-Flops (cont’d)
 D = 0, Clk High
D’
1
0
Act as inverters
D
D’
0
R
0
Hold state
Clk=1
S
D0
0
D
Q
1
D’
1
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Edge-Triggered Flip-Flops (cont’d)
 D = 1, Clk High
11 
0
D’
0
1D
D’
0
R
0
Clk=1
S
D0
0 0
1D
1
D’
1
0
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Q
Edge-Triggered Flip-Flops (cont’d)
 D = 1, Clk LOW
0
01
D’
Act as inverters
D
D’
0
0
1
R
Q
Clk=0
S
D0
1
D
0

10
1
D’
0
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Edge-Triggered Flip-Flops (cont’d)
 Positive edge-triggered
Inputs sampled on rising edge; outputs change after rising edge
 Negative edge-triggered flip-flops
Inputs sampled on falling edge; outputs change after falling edge
100
D
CLK
Qpos
Qpos'
Qneg
Qneg'
positive edge-triggered FF
negative edge-triggered FF
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Negative Edge Trigger FF in Verilog
module d_ff (q, q_bar, data, clk);
input data, clk;
output q, q_bar;
reg
q;
assign q_bar = ~q;
always @(negedge clk)
begin
q <= data;
end
endmodule
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Registers
 Collections of flip-flops with similar controls and logic
Stored values somehow related (e.g., form binary value)
Share clock, reset, and set lines
Similar logic at each stage
 Examples
Shift registers
Counters
OUT1
OUT2
OUT3
OUT4
"0"
R S
R S
R S
R S
D Q
D Q
D Q
D Q
CLK
IN1
IN2
IN3
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IN4
Shift Register
 Holds samples of input
Store last 4 input values in sequence
4-bit shift register:
OUT1
IN
D Q
D Q
OUT2
OUT3
D Q
CLK
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D Q
OUT4
Shift Register Verilog
module shift_reg (out4, out3, out2, out1,
output out4, out3, out2, out1;
input in, clk;
reg
out4, out3, out2, out1;
always @(posedge clk)
begin
out4 <= out3;
out3 <= out2;
out2 <= out1;
out1 <= in;
end
endmodule
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in, clk);
Shift Register Verilog
module shift_reg (out, in, clk);
output [4:1] out;
input in, clk;
reg
[4:1] out;
always @(posedge clk)
begin
out <= {out[3:1], in};
end
endmodule
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Universal Shift Register
 Holds 4 values
Serial or parallel inputs
Serial or parallel outputs
Permits shift left or right
Shift in new values from left or right
output
left_in
left_out
clear
s0
s1
right_out
right_in
clock
input
clear sets the register contents
and output to 0
s1 and s0 determine the shift function
s0
0
0
1
1
s1
0
1
0
1
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function
hold state
shift right
shift left
load new input
Design of Universal Shift Register
 Consider one of the four flip-flops
New value at next clock cycle:
Nth cell
to N-1th
cell
to N+1th
cell
Q
D
clear
1
0
0
0
0
s0
–
0
0
1
1
s1
–
0
1
0
1
new value
0
output
output value of FF to left (shift right)
output value of FF to right (shift left)
input
CLK
CLEAR
s0 and s1
0 1 2 3
control mux
Q[N-1]
(left)
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Input[N]
Q[N+1]
(right)
Universal Shift Register Verilog
module univ_shift (out, lo, ro, in, li, ri, s, clr, clk);
output [3:0] out;
output lo, ro;
input [3:0] in;
input [1:0] s;
input li, ri, clr, clk;
reg
[3:0] out;
assign lo = out[3];
assign ro = out[0];
always @(posedge clk or clr)
begin
if (clr) out <= 0;
else
case (s)
3: out <= in;
2: out <= {out[2:0], ri};
1: out <= {li, out[3:1]};
0: out <= out;
endcase
end
endmodule
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Counters
 Sequences through a fixed set of patterns
In this case, 1000, 0100, 0010, 0001
If one of the patterns is its initial state (by loading or
set/reset)
OUT1
IN
D Q
D Q
OUT2
OUT3
D Q
OUT4
D Q
CLK
 Mobius (or Johnson) counter
In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
OUT1
IN
D Q
D Q
OUT2
OUT3
D Q
CLK
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D Q
OUT4
Binary Counter
 Logic between registers (not just multiplexer)
XOR decides when bit should be toggled
Always for low-order bit, only when first bit is true for
second bit, and so on
OUT1
D Q
OUT2
D Q
OUT3
D Q
CLK
"1"
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OUT4
D Q
Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output out4, out3, out2, out1;
input in, clk;
reg
out4, out3, out2, out1;
always @(posedge clk)
begin
out4 <= (out1 & out2 & out3) ^ out4;
out3 <= (out1 & out2) ^ out3;
out2 <= out1 ^ out2;
out1 <= out1 ^ 1b’1;
end
endmodule
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Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output [4:1] out;
input in, clk;
reg
[4:1] out;
always @(posedge clk)
out <= out + 1;
endmodule
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Sequential Logic Summary
 Fundamental building block of circuits with state
 Latch and flip-flop
 R-S latch, R-S master/slave, D master/slave, edge-triggered D FF
 Timing methodologies
 Use of clocks
 Cascaded FFs work because prop delays exceed hold times
 Beware of clock skew
 Basic registers
 Shift registers
 Pattern detectors
 Counters
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