Transcript Typical Timing Specifications  Positive edge-triggered D flip-flop Setup and hold times Minimum clock width Propagation delays (low to high, high to low, max.

Typical Timing Specifications
 Positive edge-triggered D flip-flop
Setup and hold times
Minimum clock width
Propagation delays (low to high, high to low, max and typical)
D
CLK
Q
Tsu Th
20ns 5ns
Tsu
20ns
Th
5ns
Tw 25ns
Tplh
25ns
13ns
Tphl
40ns
25ns
all measurements are made from the clocking event that is,
the rising edge of the clock
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Cascading Edge-triggered Flip-Flops
 Shift register
New value goes into first stage
While previous value of first stage goes into second stage
Consider setup/hold/propagation delays (prop must be > hold)
IN
D Q
Q0
D Q
Q1
OUT
CLK
100
IN
Q0
Q1
CLK
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Cascading Edge-triggered Flip-Flops
 Shift register
New value goes into first stage
While previous value of first stage goes into second stage
Consider setup/hold/propagation delays (prop must be > hold)
IN
CLK
D Q
Q0
D Q
Q1
OUT
Clk1
Delay
100
IN
Q0
Q1
CLK
Clk1
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Cascading Edge-triggered Flip-Flops
(cont’d)
 Why this works
Propagation delays exceed hold times
Clock width constraint exceeds setup time
This guarantees following stage will latch current value
before it changes to new value
In
Q0
Tsu
4ns
Tsu
4ns
Tp
3ns
Q1
Tp
3ns
timing constraints
guarantee proper
operation of
cascaded components
assumes infinitely fast
distribution of the clock
CLK
Th
2ns
Th
2ns
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Clock Skew
 The problem
Correct behavior assumes next state of all storage elements
determined by all storage elements at the same time
Difficult in high-performance systems because time for clock
to arrive at flip-flop is comparable to delays through logic
(and will soon become greater than logic delay)
Effect of skew on cascaded flip-flops:
100
In
Q0
Q1
CLK1 is a delayed
version of CLK0
CLK0
CLK1
original state: IN = 0, Q0 = 1, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1
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Registers
 Collections of flip-flops with similar controls and logic
Stored values somehow related (e.g., form binary value)
Share clock, reset, and set lines
Similar logic at each stage
 Examples
Shift registers
Counters
OUT1
OUT2
OUT3
OUT4
"0"
R S
R S
R S
R S
D Q
D Q
D Q
D Q
CLK
IN1
IN2
IN3
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IN4
Shift Register
 Holds samples of input
Store last 4 input values in sequence
4-bit shift register:
OUT1
IN
D Q
D Q
OUT2
D Q
OUT3
D Q
CLK
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OUT4
Shift Register Verilog
module shift_reg (out4, out3, out2, out1,
output out4, out3, out2, out1;
input in, clk;
reg
out4, out3, out2, out1;
always @(posedge clk)
begin
out4 <= out3;
out3 <= out2;
out2 <= out1;
out1 <= in;
end
endmodule
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in, clk);
Shift Register Verilog
module shift_reg (out, in, clk);
output [4:1] out;
input in, clk;
reg
[4:1] out;
always @(posedge clk)
begin
out <= {out[3:1], in};
end
endmodule
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Universal Shift Register
 Holds 4 values
Serial or parallel inputs
Serial or parallel outputs
Permits shift left or right
Shift in new values from left or right
output
left_in
left_out
clear
s0
s1
right_out
right_in
clock
input
clear sets the register contents
and output to 0
s1 and s0 determine the shift function
s0
0
0
1
1
s1
0
1
0
1
function
hold state
shift right
shift left
load new input
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Design of Universal Shift Register
 Consider one of the four flip-flops
New value at next clock cycle:
Nth cell
to N-1th
cell
to N+1th
cell
Q
D
clear
1
0
0
0
0
s0
–
0
0
1
1
s1
–
0
1
0
1
new value
0
output
output value of FF to left (shift right)
output value of FF to right (shift left)
input
CLK
CLEAR
s0 and s1
0 1 2 3
control mux
Q[N-1]
(left)
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Input[N]
Q[N+1]
(right)
Universal Shift Register Verilog
module univ_shift (out, lo, ro, in, li, ri, s, clr, clk);
output [3:0] out;
output lo, ro;
input [3:0] in;
input [1:0] s;
input li, ri, clr, clk;
reg
[3:0] out;
assign lo = out[3];
assign ro = out[0];
always @(posedge clk or clr)
begin
if (clr) out <= 0;
else
case (s)
3: out <= in;
2: out <= {out[2:0], ri};
1: out <= {li, out[3:1]};
0: out <= out;
endcase
end
endmodule
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Counters
 Sequences through a fixed set of patterns
In this case, 1000, 0100, 0010, 0001
If one of the patterns is its initial state (by loading or
OUT1
OUT2
OUT3
OUT4
set/reset)
IN
D Q
D Q
D Q
D Q
CLK
 Mobius (or Johnson) counter
In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
OUT1
IN
D Q
D Q
OUT2
D Q
OUT3
D Q
CLK
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OUT4
Binary Counter
 Logic between registers (not just multiplexer)
XOR decides when bit should be toggled
Always for low-order bit, only when first bit is true for
second bit, and so on
OUT1
D Q
OUT2
D Q
OUT3
D Q
OUT4
D Q
CLK
"1"
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Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output out4, out3, out2, out1;
input in, clk;
reg
out4, out3, out2, out1;
always @(posedge clk)
begin
out4 <= (out1 & out2 & out3) ^ out4;
out3 <= (out1 & out2) ^ out3;
out2 <= out1 ^ out2;
out1 <= out1 ^ 1b’1;
end
endmodule
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Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output [4:1] out;
input in, clk;
reg
[4:1] out;
always @(posedge clk)
out <= out + 1;
endmodule
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Sequential Logic Summary
 Fundamental building block of circuits with state
 Latch and flip-flop
 R-S latch, R-S master/slave, D master/slave, edge-triggered D FF
 Timing methodologies
 Use of clocks
 Cascaded FFs work because prop delays exceed hold times
 Beware of clock skew
 Basic registers
 Shift registers
 Pattern detectors
 Counters
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Sequential Logic Implementation
 Models for representing sequential circuits
Finite-state machines (Moore and Mealy)
Representation of memory (states)
Changes in state (transitions)
 Design procedure
State diagrams
State transition table
Next state functions
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Abstraction of State Elements
 Divide circuit into combinational logic and state
 Localize feedback loops and make it easy to break cycles
 Implementation of storage elements leads to various
forms of sequential logic
Inputs
Combinational
Logic
State Inputs
Outputs
State Outputs
Storage Elements
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Forms of Sequential Logic
 Asynchronous sequential logic – state changes occur
whenever state inputs change (elements may be simple
wires or delay elements)
 Synchronous sequential logic – state changes occur in
lock step across all storage elements (using a periodic
waveform - the clock)
Clock
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Finite State Machine Representations
 States: determined by possible values in sequential
storage elements
 Transitions: change of state
 Clock: controls when state can change by controlling
storage elements
010
001
In = 0
 Sequential Logic
In = 1
100
111
In = 0
In = 1
110
Sequences through a series of states
Based on sequence of values on input signals
Clock period defines elements of sequence
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Example Finite State Machine Diagram
 Combination lock
ERR
closed
S1
reset
closed
mux=C1
not new
equal
& new
not equal
& new
not equal
& new
S2
S3
closed
mux=C2
not new
equal
& new
closed
mux=C3
not equal
& new
OPEN
equal
& new
open
not new
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Can Any Sequential System be
Represented with a State Diagram?
 Shift Register
Input value shown
on transition arcs
Output values shown
within state node
OUT1
0
1
0
0
0
001
D Q
110
101
0
0
1
1
1
010
1
000
D Q
OUT3
CLK
100
1
D Q
IN
OUT2
111
0
1
0
011
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1
Counters are Simple Finite State Machines
 Counters
Proceed thru well-defined state sequence in response to enable
 Many types of counters: binary, BCD, Gray-code
3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
001
000
010
011
100
3-bit up-counter
111
110
101
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Verilog Upcounter
module binary_cntr
inputs
clk;
outputs
[2:0]
reg
[2:0]
reg
[2:0]
(q, clk)
q;
q;
p;
always @(q)
//Calculate next state
case (q)
3’b000: p = 3’b001;
3’b001: p = 3’b010;
…
3’b111: p = 3’b000;
endcase
always @(posedge clk)
q <= p;
//next becomes current state
endmodule
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How Do We Turn a State Diagram into Logic?
 Counter
Three flip-flops to hold state
Logic to compute next state
Clock signal controls when flip-flop memory can change
Wait long enough for combinational logic to compute new value
Don't wait too long as that is low performance
OUT1
D Q
OUT2
D Q
CLK
"1"
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OUT3
D Q
FSM Design Procedure
 Start with counters
 Simple because output is just state
 Simple because no choice of next state based on input
 State diagram to state transition table
 Tabular form of state diagram
 Like a truth-table
 State encoding
 Decide on representation of states
 For counters it is simple: just its value
 Implementation
 Flip-flop for each state bit
 Combinational logic based on encoding
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FSM Design Procedure: State Diagram
to Encoded State Transition Table
 Tabular form of state diagram
 Like a truth-table (specify output for all input
combinations)
 Encoding of states: easy for counters – just use value
001
000
010
011
100
3-bit up-counter
111
110
101
current state
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
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next state
001
1
010
2
011
3
100
4
101
5
110
6
111
7
000
0
Implementation
 D flip-flop for each state bit
 Combinational logic based on encoding
C3
0
0
0
0
1
1
1
1
C2
0
0
1
1
0
0
1
1
C1
0
1
0
1
0
1
0
1
N3
C1
N3
0
0
0
1
1
1
1
0
C3
0
0
1
1
0
1
0
1
C2
N2
0
1
1
0
0
1
1
0
N1
1
0
1
0
1
0
1
0
N1 := C1'
N2 := C1C2' + C1'C2
:= C1 xor C2
N3 := C1C2C3' + C1'C3 + C2'C3
:= C1C2C3' + (C1' + C2')C3
:= (C1C2) xor C3
N2
C1
notation to show
function represent
input to D-FF
C3
0
1
1
0
1
0
0
1
N1
C1
C2
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C3
1
1
1
1
0
0
0
0
C2
Implementation (cont'd)
 Programmable Logic Building Block for Sequential Logic
Macro-cell: FF + logic
D-FF
Two-level logic capability like PAL (e.g., 8 product terms)
DQ
Q
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State Machine Model
 Values stored in registers represent the state of the
circuit
 Combinational logic computes:
Next state
Function of current state and inputs
Outputs
Function of current state and inputs (Mealy machine)
Function of current state only (Moore machine)
Inputs
output
logic
next state
logic
Outputs
Next State
Current State
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State Machine Model (cont’d)
 States: S1, S2, ..., Sk
 Inputs: I1, I2, ..., Im
output
logic
Inputs
Outputs
next state
logic
Next State
 Outputs: O1, O2, ..., On
Current State
 Transition function: Fs(Si, Ij)
 Output function: Fo(Si) or Fo(Si, Ij)
Next State
State
Clock 0
1
2
3
4
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5
Example: Ant Brain (Ward, MIT)
 Sensors:
 Actuators:
 Goal:
 Strategy:
L and R antennae, 1 if in touching wall
F - forward step, TL/TR - turn
left/right slightly
find way out of maze
keep the wall on the right
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Ant Brain
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Ant Behavior
A: Following wall, touching
Go forward, turning
left slightly.
If R and not L, go to A
If R and L , go to E
else go to B
C: Break in wall
Go forward, turning
right slightly
if R, go to A
if not R, stay in C
B: Following wall, not touching
Go forward, turning right
slightly
if R, go to A
if not R, go to C
E: Wall in front or on left
Turn left
If L or R, stay in E
Otherwise, go to B
LOST: Forward until we
touch something
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Designing an Ant Brain
 State Diagram
L+R
LOST
(F)
L’ R’
L+R
L’ R
L
E
(TL)
L’ R’
A
(TL, F)
R
L’ R’
B
(TR, F)
R’
R
C
(TR, F)
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R’
Synthesizing the Ant Brain Circuit
 Encode States Using a Set of State Variables
Arbitrary choice - may affect cost, speed
 Use Transition Truth Table
Define next state function for each state variable
Define output function for each output
 Implement next state and output functions using
combinational logic
2-level logic (ROM/PLA/PAL)
Multi-level logic
Next state and output functions can be optimized together
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Transition Truth Table
 Using symbolic states
and outputs
LOST
(F)
L’ R’
L+R
L+R
E
(TL)
L’ R’
L’ R
A
(TL, F)
L
R
L’ R’
state
LOST
LOST
LOST
A
A
A
B
B
...
L
0
–
1
0
0
1
–
–
...
R
0
1
–
0
1
–
0
1
...
next state
LOST
E/G
E/G
B
A
E/G
C
A
...
outputs
F
F
F
TL, F
TL, F
TL, F
TR, F
TR, F
...
B
(TR, F)
R’
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R
C
(TR, F)
R’
Synthesis
 5 states : at least 3 state variables required (X, Y, Z)
State assignment (in this case, arbitrarily chosen)
state
X,Y,Z
000
000
...
010
010
010
010
011
011
...
L R
0 0
0 1
... ...
0 0
0 1
1 0
1 1
0 0
0 1
... ...
next state
X', Y', Z'
000
001
...
011
010
001
001
100
010
...
outputs
F TR TL
1 0 0
1 0 0
...
1 0 1
1 0 1
1 0 1
1 0 1
1 1 0
1 1 0
...
it now remains
to synthesize
these 6 functions
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LOST
E
A
B
C
-
000
001
010
011
100
Synthesis of Next State and Output
Functions
state
X,Y,Z
000
000
000
001
001
001
010
010
010
011
011
100
100
inputs
L R
0 0
- 1
1 0 0
- 1
1 0 0
0 1
1 - 0
- 1
- 0
- 1
next state
X+,Y+,Z+
000
001
001
011
010
010
011
010
001
100
010
100
010
outputs
F TR TL
1 0 0
1 0 0
1 0 0
0 0 1
0 0 1
0 0 1
1 0 1
1 0 1
1 0 1
1 1 0
1 1 0
1 1 0
1 1 0
e.g.
TR = X + Y Z
X+ = X R’ + Y Z R’ = R’ TR
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Circuit Implementation
 Outputs are a function of the current state only - Moore
machine
F
TR
TL
output
logic
L
R
next state
logic
Current State
Next State
X+
Y+
Z+
X
Y
Z
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Verilog Sketch
module ant_brain (F, TR, TL, L, R)
inputs
L, R;
outputs
F, TR, TL;
reg
X, Y, Z;
assign F = function(X, Y, Z, L, R);
assign TR = function(X, Y, Z, L, R);
assign TL = function(X, Y, Z, L, R);
always @(posedge clk)
begin
X <= function (X, Y, Z, L, R);
Y <= function (X, Y, Z, L, R);
Z <= function (X, Y, Z, L, R);
end
endmodule
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Don’t Cares in FSM Synthesis
 What happens to the "unused" states (101, 110, 111)?
 Exploited as don't cares to minimize the logic
If states can't happen, then don't care what the functions do
if states do happen, we may be in trouble
L’ R’
000
(F)
L+R
L+R
101
001
(TL)
L’ R’
L’ R
010
(TL, F)
L
R
L’ R’
011
(TR, F)
110
111
Ant is in deep trouble
if it gets in this state
R’
R
100
(TR, F)
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R’
State Minimization
 Fewer states may mean fewer state variables
 High-level synthesis may generate many redundant states
 Two state are equivalent if they are impossible to distinguish
from the outputs of the FSM, i. e., for any input sequence the
outputs are the same
 Two conditions for two states to be equivalent:
 1) Output must be the same in both states
 2) Must transition to equivalent states for all input combinations
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Ant Brain Revisited
 Any equivalent states?
L+R
LOST
(F)
L’ R’
L+R
L’ R
L
E
(TL)
L’ R’
A
(TL, F)
R
R
L’ R’
B
(TR, F)
R’
C
(TR, F)
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R’
Ant Brain Revisited
Inequivalent since actions differ
L+R
LOST
(F)
L’ R’
L+R
L’ R
L
E
(TL)
L’ R’
A
(TL, F)
R
R
L’ R’
B
(TR, F)
R’
C
(TR, F)
Potentially Equivalent (actions equivalent)
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R’
Equivalence Proof
Equivalent Behavior under R
L+R
LOST
(F)
L’ R’
L+R
L’ R
L
E
(TL)
L’ R’
A
(TL, F)
R
R
L’ R’
B
(TR, F)
R’
C
(TR, F)
Equivalent Behavior under R’
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R’
New Improved Brain
 Merge equivalent B and C states
 Behavior is exactly the same as the 5-state brain
 We now need only 2 state variables rather than 3
L+R
LOST
(F)
L+R
L’ R’
L’ R
L
E
(TL)
L’ R’
A
(TL, F)
R
L’ R’
R’
B/C
(TR, F)
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New Brain Implementation
state
X,Y
00
00
00
01
01
01
10
10
10
11
11
inputs
L R
0 0
- 1
1 0 0
- 1
1 0 0
0 1
1 - 0
- 1
next state outputs
X',Y'
F TR TL
00
1 0 0
01
1 0 0
01
1 0 0
11
0 0 1
01
0 0 1
01
0 0 1
11
1 0 1
10
1 0 1
01
1 0 1
11
1 1 0
10
1 1 0
X+
L
X
0
0
0
0
1
0
0
0
1
1
1
1
Y+
1
1
0
0
R
L
X
0
1
1
1
1
0
0
0
Y
F
L
X
1
1
1
1
0
0
0
0
1
1
1
1
Y
1
1
1
1
1
0
0
1
1
0
1
1
R
Y
TR
R
L
X
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
Y
CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 61
TL
R
L
X
0
0
0
0
1
1
1
1
0
0
0
0
Y
1
1
1
1
R
Sequential Logic Implementation Summary
 Models for representing sequential circuits
Abstraction of sequential elements
Finite state machines and their state diagrams
Inputs/outputs
Mealy, Moore, and synchronous Mealy machines
 Finite state machine design procedure
Deriving state diagram
Deriving state transition table
Determining next state and output functions
Implementing combinational logic
CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 62