ECE 545 Lecture 10 Variables, Attributes, Functions and Procedures, Data Types ECE 545 – Introduction to VHDL George Mason University.

Download Report

Transcript ECE 545 Lecture 10 Variables, Attributes, Functions and Procedures, Data Types ECE 545 – Introduction to VHDL George Mason University.

ECE 545 Lecture 10

Variables, Attributes, Functions and Procedures, Data Types

ECE 545 – Introduction to VHDL

George Mason University

Resources

• Volnei A. Pedroni,

Circuit Design with VHDL

Chapter 7, Signals and Variables Chapter 11, Functions and Procedures

• Sundar Rajan,

Essential VHDL: RTL Synthesis Done Right

Chapter 11, Scalable and Parameterizable Design Chapter 12, Enhancing Design Readability and Reuse

ECE 545 – Introduction to VHDL

Combinational Logic Synthesis for Intermediates

ECE 545 – Introduction to VHDL

2-to-4 Decoder

En w

3 1 0 0 1 0 1 1 1 0 1 1 1 0 x x 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 (a) Truth table

En y

3 (b) Graphical symbol

ECE 545 – Introduction to VHDL

VHDL code for a 2-to-4 Decoder

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN En : IN y : OUT END dec2to4 ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ; STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= “0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", “1000" WHEN "111", "0000" WHEN OTHERS ; END dataflow ;

ECE 545 – Introduction to VHDL

Describing combinational logic using processes LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w En : IN : IN y : OUT END dec2to4 ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ; STD_LOGIC_VECTOR(0 TO 3) ) ; ARCHITECTURE Behavior OF dec2to4 IS BEGIN

PROCESS ( w, En )

BEGIN IF En = '1' THEN CASE w IS WHEN "00" => WHEN "01" => WHEN "10" =>

WHEN OTHERS =>

END CASE ;

ELSE

y <= "0000" ; END IF ; END PROCESS ; END Behavior ; y <= "1000" ; y <= "0100" ; y <= "0010" ; y <= "0001" ;

ECE 545 – Introduction to VHDL

Describing combinational logic using processes LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY seg7 IS PORT ( bcd leds : IN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; STD_LOGIC_VECTOR(1 TO 7) ) ; END seg7 ; ARCHITECTURE Behavior OF seg7 IS BEGIN

PROCESS ( bcd )

BEGIN CASE bcd IS WHEN "0000" => leds WHEN "0001" => leds WHEN "0010" => leds WHEN "0011" => leds WHEN "0100" => leds WHEN "0101" => leds - <= <= <= <= <= <= abcdefg "1111110" ; "0110000" ; "1101101" ; "1111001" ; "0110011" ; "1011011" ; WHEN "0110" => leds WHEN "0111" => leds WHEN "1000" => leds WHEN "1001" => leds

WHEN OTHERS

<= <= <= <=

=> leds <=

END CASE ; END PROCESS ; END Behavior ; "1011111" ; "1110000" ; "1111111" ; "1110011" ;

"-------" ;

ECE 545 – Introduction to VHDL

Describing combinational logic using processes LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY compare1 IS PORT ( A, B AeqB END compare1 ; : IN STD_LOGIC ; : OUT STD_LOGIC ) ; ARCHITECTURE Behavior OF compare1 IS BEGIN

PROCESS ( A, B )

BEGIN

AeqB <= '0' ;

IF A = B THEN

AeqB <= '1' ;

END IF ; END PROCESS ; END Behavior ;

ECE 545 – Introduction to VHDL

Incorrect code for combinational logic - Implied latch (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY implied IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END implied ; ARCHITECTURE Behavior OF implied IS BEGIN PROCESS ( A, B ) BEGIN

IF A = B THEN AeqB <= '1' ;

END IF ; END PROCESS ; END Behavior ;

ECE 545 – Introduction to VHDL

Incorrect code for combinational logic - Implied latch (2)

A B AeqB ECE 545 – Introduction to VHDL

Describing combinational logic using processes

Rules that need to be followed:

All inputs to the combinational circuit should be included in the sensitivity list No other signals should be included in the sensitivity list None of the statements within the process should be sensitive to rising or falling edges All possible cases need to be covered in the internal

and

CASE

implied latches statements in order to avoid

ECE 545 – Introduction to VHDL

Covering all cases in the IF statement

Using ELSE

IF A = B THEN

AeqB <= '1' ; ELSE AeqB <= '0' ; Using default values AeqB <= '0' ;

IF A = B THEN

AeqB <= '1' ;

ECE 545 – Introduction to VHDL

Covering all cases in the CASE statement

Using WHEN OTHERS

CASE y IS WHEN S1 => Z <= "10"; WHEN S2 => Z <= "01";

WHEN OTHERS => Z <= "00";

END CASE;

Using default values Z <= "00";

CASE y IS WHEN S1 => Z <= "10"; WHEN S2 => Z <= "10"; END CASE; CASE y IS WHEN S1 => Z <= "10"; WHEN S2 => Z <= "01"; WHEN S3 => Z <= "00";

WHEN OTHERS => Z <= „--";

END CASE;

ECE 545 – Introduction to VHDL

Combinational Logic Synthesis for Advanced

ECE 545 – Introduction to VHDL

Advanced VHDL for synthesis

For complex, generic, and/or regular circuits you may consider using PROCESSES with internal VARIABLES and FOR LOOPs

ECE 545 – Introduction to VHDL

Variables

Variable – Example (1)

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Numbits IS PORT ( X Count END Numbits ; : IN STD_LOGIC_VECTOR(1 TO 3) ; : OUT INTEGER RANGE 0 TO 3) ;

ECE 545 – Introduction to VHDL

Variable – Example (2)

ARCHITECTURE Behavior OF Numbits IS BEGIN PROCESS(X) – count the number of bits in X equal to 1 VARIABLE Tmp: INTEGER; BEGIN Tmp := 0; FOR i IN 1 TO 3 LOOP IF X(i) = ‘1’ THEN Tmp := Tmp + 1; END IF; END LOOP; Count <= Tmp; END PROCESS; END Behavior ;

ECE 545 – Introduction to VHDL

Variables - features

• • • • • Can only be declared within processes subprograms (functions & procedures) and Initial value declaration can be explicitly specified in the When assigned take an assigned value immediately Variable assignments represent the desired behavior , not the structure of the circuit Should be avoided, or at least used with caution in a synthesizable code

ECE 545 – Introduction to VHDL

Variables vs. Signals

ECE 545 – Introduction to VHDL

Variable – Example

ECE 545 – Introduction to VHDL

Incorrect Code using Signals

ARCHITECTURE Behavior OF Numbits IS SIGNAL Tmp : INTEGER RANGE 0 TO 3 ; BEGIN PROCESS(X) – count the number of bits in X equal to 1 BEGIN Tmp <= 0; FOR i IN 1 TO 3 LOOP IF X(i) = ‘1’ THEN Tmp <= Tmp + 1; END IF; END LOOP; Count <= Tmp; END PROCESS; END Behavior ;

ECE 545 – Introduction to VHDL

N-bit NAND

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY NANDn IS GENERIC (n: INTEGER := 8) PORT ( X : IN STD_LOGIC_VECTOR(1 TO n); Y : OUT STD_LOGIC); END NANDn;

ECE 545 – Introduction to VHDL

N-bit NAND architecture using variables

ARCHITECTURE behavioral1 OF NANDn IS BEGIN PROCESS (X)

VARIABLE Tmp: STD_LOGIC;

BEGIN Tmp

X(1); AND_bits: FOR i IN 2 TO n LOOP Tmp

Tmp AND X( i ) ; END LOOP AND_bits ; Y <= NOT Tmp ; END PROCESS; END behavioral1 ;

ECE 545 – Introduction to VHDL

Incorrect N-bit NAND architecture using signals

ARCHITECTURE behavioral2 OF NANDn IS SIGNAL Tmp: STD_LOGIC; BEGIN PROCESS (X) BEGIN Tmp <= X(1); AND_bits: FOR i IN 2 TO n LOOP Tmp <= Tmp AND X( i ) ; END LOOP AND_bits ; Y <= NOT Tmp ; END PROCESS; END behavioral2 ;

ECE 545 – Introduction to VHDL

Correct N-bit NAND architecture using signals

ARCHITECTURE dataflow1 OF NANDn IS SIGNAL Tmp: STD_LOGIC_VECTOR(1 TO n); BEGIN

Tmp(1)

<= X(1); AND_bits:

FOR i IN 2 TO n GENERATE Tmp(i)

Tmp(i-1)

AND X( i ) ; END LOOP AND_bits ; Y <= NOT Tmp(n) ; END dataflow1 ;

ECE 545 – Introduction to VHDL

Correct N-bit NAND architecture using signals

ARCHITECTURE dataflow2 OF NANDn IS SIGNAL Tmp: STD_LOGIC_VECTOR(1 TO n); BEGIN Tmp <= (OTHERS => 1); Y <= ‘0’ WHEN X = Tmp ELSE ‘1’; END dataflow2 ;

ECE 545 – Introduction to VHDL

Parity generator entity

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY oddParityLoop IS GENERIC ( width : INTEGER := 8 ); PORT ( ad : in STD_LOGIC_VECTOR (width - 1 DOWNTO 0); oddParity : out STD_LOGIC ) ; END oddParityLoop ;

ECE 545 – Introduction to VHDL

Parity generator architecture using signals

ARCHITECTURE dataflow OF oddParityGen IS SIGNAL genXor: STD_LOGIC_VECTOR(width DOWNTO 0); BEGIN

genXor(0)

<= '0'; parTree:

FOR i IN 1 TO width GENERATE genXor(i)

genXor(i - 1)

END GENERATE; XOR ad(i - 1); oddParity <= genXor(width) ; END dataflow ;

ECE 545 – Introduction to VHDL

Parity generator architecture using variables

ARCHITECTURE behavioral OF oddParityLoop IS BEGIN

PROCESS (ad) VARIABLE loopXor: STD_LOGIC;

BEGIN

loopXor

:= '0';

FOR i IN 0 to width -1 LOOP loopXor

loopXor

XOR ad( i ) ; END LOOP ; oddParity <= loopXor ; END PROCESS; END behavioral ;

ECE 545 – Introduction to VHDL

Sequential Logic Synthesis for Beginners

ECE 545 – Introduction to VHDL

For Beginners

Use processes with very simple structure only to describe - registers - shift registers - counters - state machines.

Use examples discussed in class as a template.

Create

generic

entities for registers, shift registers, and counters, and instantiate the corresponding components in a higher level circuit using GENERIC MAP PORT MAP.

Supplement sequential components with combinational logic described using concurrent statements.

ECE 545 – Introduction to VHDL

Sequential Logic Synthesis for Intermediates

ECE 545 – Introduction to VHDL

For Intermmediates

Use Processes with IF and CASE statements only. Do not use LOOPS or VARIABLES.

Sensitivity list of the PROCESS should include

only

signals that can by themsleves change the outputs of the sequential circuit (typically, clock and asynchronous set or reset) Do not use PROCESSes without sensitivity list (they can be synthesizable, but make simulation inefficient)

ECE 545 – Introduction to VHDL

Constrained Array Types

ECE 545 – Introduction to VHDL

One-dimensional arrays – Examples (1)

type

word_asc

is array

31)

of std_logic

;

type

word_desc

array(31

downto

std_logic; …..

signal

buffer_register: word_desc; …..

buffer_register(6) <= ‘1’; …..

variable

tmp : word_asc; …..

tmp(5):= ‘0’;

ECE 545 – Introduction to VHDL

One-dimensional arrays – Examples (2)

type

controller_state

(initial, idle, active, error);

type

state_counts_imp

is array

(

idle to error

)

natural;

type

state_counts_exp

is array( controller_state range idle to error

)

natural;

type

state_counts_full

is array

(

controller_state

)

natural; …..

variable counters: state_counts_exp; …..

counters(active) := 0; …..

counters(active) := counters(active) + 1;

ECE 545 – Introduction to VHDL

Unconstrained Array Types

ECE 545 – Introduction to VHDL

Predefined Unconstrained Array Types

Predefined

bit_vector string array of bits array of characters

Defined in the ieee.std_logic_1164 package:

std_logic_vector array of std_logic_vectors

ECE 545 – Introduction to VHDL

Predefined Unconstrained Array Types

subtype

….

byte

bit_vector(7

downto

0);

variable

….

channel_busy : bit_vector(1

4);

constant

….

ready_message :string := “ready”;

signal

memory_bus: std_logic_vector (31

downto

0);

ECE 545 – Introduction to VHDL

User-defined Unconstrained Array Types

type

sample

is array

integer; (natural

range

<>)

….

variable

….

long_sample

sample(0 to 255);

constant

look_up_table_1: sample := (127, -45, 63, 23, 76); ….

ECE 545 – Introduction to VHDL

Attributes of Arrays and Array Types

ECE 545 – Introduction to VHDL

Array Attributes

A’left(N) A’right(N) A’low(N) A’high(N) left bound of index range of dimension N of A right bound of index range of dimension N of A lower bound of index range of dimension N of A upper bound of index range of dimension N of A A’range(N) A’reverse_range(N) reversed index range of dimension N of A A’length(N) index range of dimension N of A length of index range of dimension N of A A’ascending(N) true if index range of dimension N of A is an ascending range, false otherwise

ECE 545 – Introduction to VHDL

Array Attributes - Examples

type

is array

4, 31

downto

0); A’left(1) A’right(2) A’low(1) A’high(2) A’range(1) A’length(2) A’ascending(2)

ECE 545 – Introduction to VHDL

= 1 = 0 = 1 = 31 = 1

4 = 32 = false 44

ECE 545 – Introduction to VHDL

Subprograms

• • • • • • Include

functions

and

procedures

Commonly used pieces of code Can be placed in a library, and then reused and shared among various projects Abstract operations that are repeatedly performed Type conversions Use only sequential statements, the same as processes

ECE 545 – Introduction to VHDL

Typical locations of subprograms

FUNCTION / PROCEDURE PACKAGE PACKAGE BODY

global

LIBRARY ENTITY

local for all architectures of a given entity ECE 545 – Introduction to VHDL

ARCHITECTURE Declarative part

local for a given architecture

ECE 545 – Introduction to VHDL

Functions

Functions – basic features

• Functions always return a single value as a result • • • • Are called using formal and actual parameters the same way as components never modify parameters passed to them parameters can only be constants (including generics) and signals (including ports); variables are not allowed; the default is a CONSTANT when passing parameters, no range specification should be included (for example no RANGE for INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR) • are always used in some expression, and not called on their own

ECE 545 – Introduction to VHDL

Function syntax

FUNCTION function_name () RETURN data_type IS [declarations] BEGIN (sequential statements) END function_name;

ECE 545 – Introduction to VHDL

Function parameters - example

FUNCTION f1 (a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR) RETURN BOOLEAN IS BEGIN (sequantial statements) END f1;

ECE 545 – Introduction to VHDL

Function calls - examples

x <= conv_integer(a); IF x > maximum(a, b) THEN ....

WHILE minimum(a, b) LOOP .......

ECE 545 – Introduction to VHDL

Function – Example 1

LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE my_package IS FUNCTION log2_ceil (CONSTANT s: INTEGER) RETURN INTEGER; END my_package; PACKAGE body my_package IS FUNCTION log2_ceil (CONSTANT s: INTEGER) RETURN INTEGER IS VARIABLE m,n : INTEGER; BEGIN m := 0; n := 1; WHILE (n < s) LOOP m := m + 1; n := n*2; END LOOP; RETURN m; END log2_ceil; END my_package;

ECE 545 – Introduction to VHDL

Function call – Example 1

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE work.my_package.all; ENTITY log2_int IS

GENERIC (m

: INTEGER :=20); PORT (x: IN STD_LOGIC_VECTOR(3 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END log2_int; ARCHITECTURE log2_int OF log2_int IS

CONSTANT

l2m : INTEGER := log2_ceil (

); SIGNAL r : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN r <= conv_std_logic_vector(l2m,4); y <= x*r; END log2_int;

ECE 545 – Introduction to VHDL

Function – Example 2

library IEEE; use IEEE.std_logic_1164.all; ENTITY powerOfFour IS

PORT ( X

: IN INTEGER; ); Y : OUT INTEGER; END powerOfFour;

ECE 545 – Introduction to VHDL

Function – Example 2

ARCHITECTURE behavioral OF powerOfFour IS FUNCTION Pow (

SIGNAL

RETURN INTEGER IS N:INTEGER; Exp : INTEGER) VARIABLE Result : INTEGER := 1; BEGIN FOR i IN 1 TO Exp LOOP Result := Result * N; END LOOP; RETURN( Result ); END Pow; BEGIN Y <=

Pow ( X

, 4); END behavioral;

ECE 545 – Introduction to VHDL

Package containing a function (1)

LIBRARY IEEE; USE IEEE.std_logic_1164.all; PACKAGE specialFunctions IS FUNCTION Pow( SIGNAL N: INTEGER; Exp : INTEGER) RETURN INTEGER; END specialFunctions

ECE 545 – Introduction to VHDL

Package containing a function (2)

PACKAGE BODY specialFunctions IS FUNCTION Pow(SIGNAL N: INTEGER; Exp : INTEGER) RETURN INTEGER IS VARIABLE Result : INTEGER := 1; BEGIN FOR i IN 1 TO Exp LOOP Result := Result * N; END LOOP; RETURN( Result ); END Pow; END specialFunctions

ECE 545 – Introduction to VHDL

Type conversion function (1)

LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------------------------------------------------------ PACKAGE my_package IS FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR) RETURN INTEGER; END my_package; -------------------------------------------------------------------------------------------------

ECE 545 – Introduction to VHDL

Type conversion function (2)

PACKAGE BODY my_package IS FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR) RETURN INTEGER; VARIABLE result: INTEGER RANGE 0 TO 2**vector’LENGTH - 1; VARIABLE carry: STD_LOGIC; BEGIN IF(vector(vector’HIGH)=‘1’ THEN result:=1; ELSE result := 0; FOR i IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP result := result*2; IF (vector(i) = ‘1’) THEN result := result+1; END IF; RETURN result; END conv_integer; END my_package;

ECE 545 – Introduction to VHDL

Type conversion function (3)

LIBRARY ieee; USE ieee.std_logic_1164.all;

USE work.my_package.all;

------------------------------------------------------------------------------------------------ ENTITY conv_int2 IS PORT ( a: IN STD_LOGIC_VECTOR (3 DOWNTO 0); y: OUT INTEGER RANGE 0 TO 15); END conv_int2; ------------------------------------------------------------------------------------------------ ARCHITECTURE my_arch OF conv_int2 IS BEGIN y <= conv_integer(a); END my_arch;

ECE 545 – Introduction to VHDL

Procedures

Procedures – basic features

• Procedures

do not return a value

• • • • • are called using formal and actual parameters the same way as components

may modify parameters

passed to them

each parameter must have a mode: IN, OUT, INOUT parameters can be

constants (including generics), signals (including ports), and

variables;

the default for inputs (mode in) is a constant, the

default for outputs (modes out and inout) is a variable

when passing parameters,

range specification should be included

(for example RANGE for INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR) •

Procedure calls are statements on their own

ECE 545 – Introduction to VHDL

Procedure syntax

PROCEDURE procedure_name () IS [declarations] BEGIN (sequential statements) END function_name;

ECE 545 – Introduction to VHDL

Procedure parameters - example

FUNCTION f1 (a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR) RETURN BOOLEAN IS BEGIN (sequantial statements) END f1;

ECE 545 – Introduction to VHDL

Procedure calls - examples

compute_min_max(in1, in2, in3, out1, out2); divide(dividend, divisor, quotient, remainder); IF (a > b) THEN compute_min_max(in1, in2, in3, out1, out2); .......

ECE 545 – Introduction to VHDL

Procedure – example (1)

LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.decProcs.all; ENTITY decoder IS port ( decIn: IN STD_LOGIC_VECTOR(1 DOWNTO 0); decOut: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END decoder;

ECE 545 – Introduction to VHDL

Procedure – example (2)

ARCHITECTURE simple OF decoder IS PROCEDURE DEC2x4 (inputs : in STD_LOGIC_VECTOR(1 downto 0); decode: out STD_LOGIC_VECTOR(3 downto 0) ) IS BEGIN CASE inputs IS WHEN "11" => decode := "1000"; WHEN "10" => decode := "0100"; WHEN "01" => decode := "0010"; WHEN "00" => decode := "0001"; WHEN others => decode := "0001"; END case; END DEC2x4; BEGIN DEC2x4(decIn,decOut); END simple;

ECE 545 – Introduction to VHDL

Operators

Operator as a function (1)

LIBRARY ieee; USE ieee.std_logic_1164.al; ------------------------------------------------------------------------------------------------ PACKAGE my_package IS FUNCTION "+" (a, b: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; END my_package; -------------------------------------------------------------------------------------------------

ECE 545 – Introduction to VHDL

Operator as a function (2)

PACKAGE BODY my_package IS FUNCTION "+" (a, b: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; VARIABLE result: STD_LOGIC_VECTOR; VARIABLE carry: STD_LOGIC; BEGIN carry := ‘0’; FOR i IN a’REVERSE_RANGE LOOP result(i) := a(i) XOR b(i) XOR carry; carry := (a(i) AND b(i)) OR (a(i) AND carry) OR (b(i) AND carry)); END LOOP; RETURN result; END "+" ; END my_package;

ECE 545 – Introduction to VHDL

Operator Overloading

ECE 545 – Introduction to VHDL

Operator overloading

• • • Operator overloading allows different argument types for a given operation (function) The VHDL tools resolve which of these functions to select based on the types of the inputs This selection is transparent to the user as long as the function has been defined for the given argument types.

ECE 545 – Introduction to VHDL

Different declarations for the same operator Example

Declarations in the package ieee.std_logic_unsigned:

function “+” ( L: std_logic_vector; R:std_logic_vector) return std_logic_vector; function “+” ( L: std_logic_vector; R: integer) return std_logic_vector; function “+” ( L: std_logic_vector; R:std_logic) return std_logic_vector;

ECE 545 – Introduction to VHDL

Different declarations for the same operator Example signal count: std_logic_vector(7 downto 0); You can use: count <= count + “0000_0001”;

count <= count + 1;

count <= count + ‘1’;

ECE 545 – Introduction to VHDL

VHDL as a Strongly Typed Language

ECE 545 – Introduction to VHDL

Notion of

type

• • • • • Type defines a set of values and a set of applicable operations Declaration of a type determines which values can be stored in an object (signal, variable, constant) of a given type Every object can only assume values of its nominated type Each operation (e.g., and, +, *) includes the types of values to which the operation may be applied, and the type of the result The goal of strong typing is a detection of errors at an early stage of the design process

ECE 545 – Introduction to VHDL

Example of strong typing

architecture

incorrect

example1

is type type

apples

is range

0 oranges

is range to

0 100;

100;

signal signal

apple1: apples; orange1: oranges;

begin

apple1 <= orange1;

end

incorrect;

ECE 545 – Introduction to VHDL

Type Classification

ECE 545 – Introduction to VHDL

Classification of data types

ECE 545 – Introduction to VHDL

Integer Types

Integer type

Name: Status: integer predefined Contents:

all integer numbers representable on a particular host computer, but

at least

numbers in the range

–(2 31 -1) .. 2 31 -1

ECE 545 – Introduction to VHDL

User defined

integer types - Examples

type

day_of_month

is range

; type

year

is range

2100;

type

set_index_range

is range

999

downto

100;

constant

number_of_bits: integer :=32;

type

bit_index

is range

number_of_bits-1; Values of bounds can be expressions, but need to be known when the model is analyzed.

ECE 545 – Introduction to VHDL

Enumeration Types

ECE 545 – Introduction to VHDL

Predefined

enumeration types (1)

boolean

(true, false)

bit

(‘0’, ‘1’)

character VHDL-87:

128 7-bit ASCII characters

VHDL-93:

256 ISO 8859 Latin-1 8-bit characters

ECE 545 – Introduction to VHDL

Predefined

enumeration types (2)

severity_level

(note, warning, error, failure)

Predefined in VHDL-93 only: file_open_kind

(read_mode, write_mode, append_mode)

file_open_status

(open_ok, status_error, name_error, mode_error)

ECE 545 – Introduction to VHDL

User-defined

enumeration types Examples

type

state

(S0, S1);

type

alu_function

(disable, pass, add, subtract, multiply, divide);

type

octal_digit

(‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’);

type

mixed

(lf, cr, ht, ‘-’, ‘/‘, ‘\’);

Each value in an enumeration type must be either an identifier or a character literal

ECE 545 – Introduction to VHDL

Floating-Point Types

ECE 545 – Introduction to VHDL

Floating point types

• • • Used to represent real numbers Numbers are represented using a significand (mantissa) part and an exponent part Conform to the IEEE standard 754 or 854 Minimum size of representation that must be supported by the implementation of the VHDL standard:

VHDL-2001: VHDL-87, VHDL-93:

64-bit representation 32-bit representation

ECE 545 – Introduction to VHDL

Real literals - examples

23.1

46E5 1E+12 1.234E09

34.0e-08 23.1

46  10 5 1  10 12 1.234  10 9 34.0  10 -8 2#0.101#E5 8#0.4#E-6 16#0.a5#E-8 0.101

2  0.4

8  8 -6 2 5 =(2 = (4  -1 8 +2 -1 ) -3  ) 8  -6 2 5 0.a5

16  16 -8 =(10  16 -1 +5  16 -2 )  16 -8

ECE 545 – Introduction to VHDL

The ANSI/IEEE standard floating-point number representation formats

ECE 545 – Introduction to VHDL

User-defined

floating-point types Examples

type

input_level

is range

-10.0

+10.0

type

probability

is range

0.0

1.0;

constant

max_output: real := 1.0E6;

constant

min_output: real := 1.0E-6;

type

output_range

max_output

downto

min_output;

ECE 545 – Introduction to VHDL

Attributes of Scalar Types

ECE 545 – Introduction to VHDL

Attributes of all scalar types

T’left T’right T’low T’high

first (leftmost) value in T last (rightmost) value in T least value in T greatest value in T

Not available in VHDL-87: T’ascending true

if T is an ascending range,

false

otherwise

T’image(x)

a string representing the value of x

T’value(s)

the value in T that is represented by s

ECE 545 – Introduction to VHDL

Attributes of all scalar types - examples

type

index_range

is range

downto

11; index_range’left index_range’right index_range’low index_range’high index_range’ascending index_range’image(14) index_range’value(“20”) = 21 = 11 = 11 = 21 = false = “14” = 20

ECE 545 – Introduction to VHDL

Attributes of discrete types

T’pos(x) T’val(n) T’succ(x) T’pred(x) T’leftof(x) T’rightof(x)

position number of x in T value in T at position n value in T at position one greater than position of x value in T at position one less than position of x value in T at position one to the left of x value in T at position one to the right of x

ECE 545 – Introduction to VHDL

Attributes of discrete types - examples

type

logic_level

(unknown, low, undriven, high); logic_level’pos(unknown) = 0 logic_level’val(3) = high logic_level’succ(unknown) = low logic_level’pred(undriven) logic_level’leftof(unknown) = low logic_level’rightof(undriven) = high

error

ECE 545 – Introduction to VHDL

Subtypes

Subtype

• • • • Defines a subset of a base type values A condition that is used to determine which values are included in the subtype is called a constraint All operations that are applicable to the base type also apply to any of its subtypes Base type and subtype can be mixed in the operations , but the result must belong to the subtype, otherwise an error is generated.

ECE 545 – Introduction to VHDL

Predefined subtypes

natural positive integers



0 integers > 0 Not predefined in VHDL-87: delay_length time



ECE 545 – Introduction to VHDL

100

User-defined subtypes - Examples

subtype

bit_index

integer

range

downto

subtype

input_range

1.0E+12; real

range

1.0E-9

ECE 545 – Introduction to VHDL

101

ECE 545 – Introduction to VHDL

Operators

102

Operators (1)

ECE 545 – Introduction to VHDL

103

Operators (2)

ECE 545 – Introduction to VHDL

104

Operators (3)

ECE 545 – Introduction to VHDL

105