Anasim Corporation Technology, Methodology, PI-FP Environment and Examples Raj Nair Sept. 22, 2008 Presentation Overview Background and history Methodology & technology fundamentals -fp Customer chip / illustrative examples Floorplanning.
Download ReportTranscript Anasim Corporation Technology, Methodology, PI-FP Environment and Examples Raj Nair Sept. 22, 2008 Presentation Overview Background and history Methodology & technology fundamentals -fp Customer chip / illustrative examples Floorplanning.
Anasim Corporation Technology, Methodology, PI-FP Environment and Examples Raj Nair Sept. 22, 2008 Presentation Overview Background and history Methodology & technology fundamentals -fp Customer chip / illustrative examples Floorplanning / optimization discussion Tool demo (as possible) Key messages of interest September 2008 AnaSIM 2 Power Integrity Challenges: CPU Transistors double every ~18 months Power (Watts) 100 1 486 286 10 8086 8085 8080 Power doubles every ~36 months Pentium® processors Processor power doubles every ~36 months… 386 8008 4004 0.1 ’71 CPU Operating State Currents (Amp) Operating modes create load shifts +30.00u +30.00u +30.01u +30.01u +30.02u +60.00 +30.02u ’74 +30.03u ’85 ’92 ’00 Volts (V) +30.00u +30.05u +30.10u +30.15u +1.00 Active +40.00 +500.00m +20.00 ’04 ’08 CPU On-Chip Voltage Droops Time (s) +30.03u ’78 Sleep Voltage Droops Blue Screens! 0.0 Time(s) Which create supply voltage ‘droops’ Microprocessor Heat Spreader Package Managed by Substrate package Mother Board Capacitors (Original figure from C. Baldwin) devices Pentium™ is a trademark of Intel® Corporation September 2008 AnaSIM 3 Package CAP Loop-L scaling Load shift induced voltage noise equation and derivation of package component characteristics scaling Lp sin( t ) e t Ir V f Vi I 1 s Cd Cd V1 kvV1 I1 1 Sl Sc S 2f L1 C1V12 f1 L1 ki C1 V1 C1 and V2 kvV2 I 2 Inversely related to process scaling (on-die cap) & (freq. scaling)2 L2 C2V22 f1 L2 ki C2 V2 C2 10 1 0.1 Q-scaling References: 0.01 Nair P858 2001 Intel Assembly Technology Journal – Invited Paper on ‘Pathfinding’ 2002 Intel Technology Journal paper “Emerging Directions for Packaging…” September 2008 gives Quintuplet and Triplet loop-L scaling loop-L, pH V I Lp AnaSIM T-scaling <<0.1pH! P860 P1262 Process P1264 65nm 4 On-die L & L*di/dt challenge Consider a Roots of Two Scaling [1] scenario: Capacitance-per-unit-area, Ca, scales by 2 , operating voltage scales by 1 , frequency 2 scales by 2 , and chip area scales by 1 2 . Following this constant-power scaling direction, and inspecting the change in Dynamic Voltage Droop in a unit area (/ua) of integrated silicon, we get: Since C/ua scales by 1 2 and voltage scales by , I scales by 2* 2. 2 Assuming the effective L/ua doesn't change, Multiplying I and I L reduces by a factor of C 1 . 2 L in the scaled process generation, the dynamic voltage droop amplitude: C L scales by C 2* 2* 1 , or by a factor of 2 for constant power scaling. 2 References: Nair, Nair & Bennett, 2008 EDADesignline® publications “A Power Integrity Wall follows the Power Wall” & “Dynamic Voltage Droops & Total PI” September 2008 AnaSIM 5 Challenge Atomic or Abstract? Polygonal Analyses AnaSIM Nanoscale IC’s face exploding, exponential computation complexity Energy & Efficiency September 2008 Analyze ripples by molecular interactions? Must know IC’s ripples 6 Meeting the Challenge Differential Power ECD: Continuum models AnaSIM Grid is uniform; treat as a voltage-continuum along a single surface USPTO PUB Include R, L, C and solve ‘true-electromagnetically’ Abstract silicon, package September 2008 Voltage is a potential difference; treat power grid differentially Partition hierarchically & exploit symmetry Include distributed models for silicon loads, CAP, pkg and board components 7 Abstraction & Physics-based Sims High levels of Abstraction Comprehensive Modeling AnaSIM All grid electromagnetic properties, R, L, C used Actual block load current profiles used; di/dt, load activity factors included Physics based Simulation September 2008 Power GRID as SURFACE DISTRIBUTED circuit load currents & capacitance SYMMETRY in physical as well as electrical aspects Field solver employed for Maxwell’s equations on ‘surfaces’ / NO ‘models’ 8 On-Die CAP for Noise Reduction With Die Caps Without Die Caps Simple, lumped SPICE analyses indicate On-Die CAP helps in ΔVCC reduction Area cost, Gate Oxide leakage are concerns Reference: Narendra, ICCAD ‘03 September 2008 AnaSIM 9 SoC Power Integrity Simulation R+L+C Dynamic Noise Simulation in -fp 9 x 7mm chip Differential noise 5nF /sq. cm distributed CAP Explicit CAP LENS 100mA peak noise pulse of 100ps width Pulse noise source Power grid simulation Do CAPACITORS really absorb noise energy? Source: D. Bennett, ANASIM Corp., September 2008 -fp power integrity aware floor planner, Use slide show AnaSIM www.anasim.com Animation slide 10 Resonant effects; More / Less CAP? Single active circuit block in a 4x4mm IC resonance -fp what-if experiments showing effect of gate switching time and on-chip de-cap on maximum voltage droop. AnaSIM September 2008 11 PI-FP Tool Environment Simulation netlist .TRAN 200e-12 .PLOT 20 .ACC 0.0060 .PRINTNODE ALL Ggrid1 0.2 0.2 0.0005 0.0080 0.030 10e-9 10e-9 Igrid1 0.1 0.1 0.02 0.02 pulse.txt 1 Ttline1 1 2 0.01 10e-9 100e-12 0.3 Ngrid1 1 0.11 0.11 pulse.txt : Current Source 0 22E-12 40E-12 60E-12 80E-12 100E-12 120E-12 140E-12 160E-12 180E-12 200E-12 September 2008 AnaSIM 0 0.030901699 0.058778525 0.080901699 0.095105652 0.1 0.095105652 0.080901699 0.058778525 0.030901699 0 12 PI-FP Tool Environment contd. Multi-Grid design Planar or 3D AnaSIM Include multiple chips in stacked or planar design Code efficiency September 2008 L calculation Each GRID on its own core (CPU) 13 Non-disruptive, Complementary Anasim’s -fp bridges PI gap Complements, not Win-Win-Win: User, compete with or replace traditional IC analysis! EDA partner & Anasim Optimization and front-end planning Reduces cost: cuts onchip or on-pkg CAP September 2008 Minimizes costly design iterations AnaSIM Results in MINUTES 14 Example: System-level Chip Sim GUI or Netlist capture Experiment-1 results -fp simulation schematic illustration (hyperlinked image) September 2008 AnaSIM Chip NETLIST Load current profiles are pulse100gap100 and pulse200gap200 SYMMETRY in physical as well as electrical aspects Chip grid ANIMATION & Mirror Notice substantial voltage variation of top left corner Cap 200pF added: results Chip grid ANIMATION & Mirror 15 Advanced SiP Simulation Near load systems Active Noise Regulator* Distributed Local (POL) Voltage Regulators Chip power grid noise Spatial & Temporal Power supply variation in x, y and t Data can feed into future Dynamic Timing Analysis? Simulation speed allows ‘what-if’ experiments for optimization Reference: ANR attached to top left corner * Nair & Bennett, ComLSI Power Management Designline article http://www.powermanagementdesignline.com/howto/175800373 September 2008 Use slide show AnaSIM Animation slide of grid 16 Customer Chip: CAP & Noise Analysis on a CLOCK chip Corner CAPs connected to IO Ring Corner CAPs connected to Core Grid CAPACITOR blocks from IO ring corners connected into Core power grid increased noise in the core grid Source: ComLSI, Inc. www.comlsi.com September 2008 AnaSIM 17 IO Ring impact on Core Noise Analysis on a customer CLOCK chip The voltage regulators, connecting between the IO Ring and the Core Grid are seen to become significant noise injection nodes with the inclusion of loads and the IO Ring. Pictures above are snapshots of dynamic plots. September 2008 AnaSIM 18 Customer chip Grid R, L + C Design Maximum noise with grid wire width, 3nf cap 300 Noise at 10u wire width and varied on-chip cap 200 250 175 Noise (mv) 200 150 150 100 125 50 100 Noise (mv) 2 0 5 20 10 30 40 3 4 5 On-chip CAP (nf) 50 Wire width (microns) With fixed on-chip capacitance value, increase in grid wire width (reduction in resistance with minimal benefit in inductance) reduces noise to a point Increase in capacitance on-die has sub-linear benefit in noise reduction; more CAP is not always good… September 2008 AnaSIM 19 Power Gating & Noise Flow Power Gating transforms preferred pathways for noise flow in addition to transient noise generation due to large switched capacitances… Source: ANASIM Corp., September 2008 -fp power integrity aware floor planner, www.anasim.com AnaSIMslide Animation 20 Floorplanning / Optimization GRID wire width, spacing, pitch DECAP optimization Area savings Block placement tweaks for PI Metal resource savings, routing / timing facilitation Noise generation, propagation Chip-Package co-simulation Operating voltage (Energy) tuning Resonance detection and avoidance… September 2008 AnaSIM 21 Anasim Info Incorprated in 2006 Core expertise: Power Integrity Spin-off from ComLSI (2003 incorporation) Analog, Mixed-Signal design services, consulting, IP in signaling and power management -fp, PI methodology & consulting IP: Effective Current Density (ECD), pat. pend. Vision “Complete simulation through continuum models” Total Power Integrity (TPI) inclusion into chip / system design September 2008 AnaSIM 22 Core Anasim Team (75 yrs+) CXO: Raj Nair Chief Scientist: Dr. Donald Bennett Founded ComLSI in 2003, successfully creating, patenting and licensing Silicon IP (12 patents, 4 issued) in power integrity / multimedia data communications, 22+ years in industry & academia, 40+ total patents, prior corporate experience at Intel, Larsen & Toubro, ~6 years of low-burnrate startup experience. Founded QuantumDA in 2003, developing RLCSim, GRID simulation suite, EDA Director at ComLSI, 15 years prior corporate experience in semiconductor device physics, IC design at ST Micro. GUI Architect: Malcolm White 38+ years in semiconductor physical design and CAD software, Serial entrepreneur, ComLSI PD architect, corporate: Intel, Mentor. September 2008 AnaSIM 23 Milestones to-date Chip Floorplan ‘true-electromagnetic’ simulation Stand-alone Tool released to market (2008) Patent pending algorithm – ECD Front-end chip floorplan optimization now feasible. GUI, Simulator, Input language, Results Viewer & DEMO Close to signing on a Japanese distributor Industry Validation ongoing Anasim white papers top three of EDA Designline’s highest user-rated papers; SoC2007, Nanotech 2008 and NanoEquity 2008 invited presentations Compiling a book on Power Integrity (PI), Prentice Hall™ September 2008 AnaSIM 24 Summary Anasim bringing sea change into SoC methodology with physics-based analyses and high levels of abstraction Benefits to chip resource usage, area, energy, performance, and total design effort Non-disruptive, Win-Win-Win engagement Fills the GAP in Total Power Integrity analyses Links, tel. [email protected] +1 480-694-5984 Anasim White Papers pifp1.pdf, pifp2.pdf, pifp3.pdf Product - -fp brochure ComLSI, parent co. September 2008 AnaSIM 25